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MIC3002 fom management ic with internal calibration micrel inc. ? 2180 fort une drive ? san jose, ca 95131 ? usa ? tel +1 (408) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com july 2007 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 general description the MIC3002 is a fiber optic module controller which enables the implementation of sophisticated, hot - pluggable fiber optic transceivers with intelligent laser control and an internally calibrated digital diagn ostic monitoring interface per sff - 8472. it essentially integrates all non - datapath functions of an sfp transceiver into a tiny (4mm x 4mm) qfn package. it also works well as a microcontroller peripheral in transponders or 10gbps transceivers. a highly con figurable automatic power control (apc) circuit controls laser bias. bias and modulation are temperature compensated using dual dacs, an on - chip temperature sensor, and nvram look - up tables. a programmable internal feedback resistor provides a wide dynamic range for the apc. controlled laser turn - on facilitates hot plugging. an analog - to - digital converter converts the measured temperature, voltage, bias current, transmit power, and received power from analog to digital. an eepot provides front - end adjustmen t of rx power. each parameter is compared against user - programmed warning and alarm thresholds. analog comparators and dacs provide high - speed monitoring of received power and critical laser operating parameters. data can be reported as either internally c alibrated or externally calibrated. an interrupt output, power - on hour meter, and data - ready bits add user friendliness beyond sff - 8472. the interrupt output and data - ready bits reduce overhead in the host system. the power - on hour meter logs operating hou rs using an internal real - time clock and stores the result in nvram. in addition to the features listed above which are already implemented in the previous controller mic3001, the MIC3002 features an extensive temperature range, options to mask alarms and warnings interrupt and txfault, and ability to support up to four chips with the same address on the serial interface. communication with the MIC3002 is via an industry standard 2 - wire serial interface. nonvolatile memory is provided for serial id, configu ration, and separate oem and user scratchpad spaces. two - level password protection guards against data corruption. features ? extensive temperature range ? alarms and warnings interrupt and txfault masks ? capability to support up to four c hips on the serial interface ? lut to compensate for chip - fom case temperature difference ? apc or constant - current laser bias ? turbo mode for apc loop start - up and shorter laser turn on time ? supports multiple laser types and bias circuit topologies ? integrated digital temperature sensor ? temperature compensation of modulation, bias, and fault levels via nvram look - up tables ? nvram to support gbic/sfp serial id function ? user writable eeprom scratchpad ? diagnostic monitoring interface per sff - 8472 ? monitors and reports critical parameters: temperature, bias current, tx and rx optical power, and supply voltage ? s/w control and monitoring of txfault, rxlos, rateselect, and txdisable ? internal or external calibration ? eepot for adjusting rx power measurement ? power - on hour meter ? interrupt capability ? extensive test and calibration features ? 2 - wire smbus - compatible serial interface ? sfp/sfp+ msa and sff - 8472 compliant ? 3.0v to 3.6v power supply range ? 5v - tolerant i/o ? available in (4mm x 4mm) 24 - pin qfn package applications ? sfp/sfp+ optical transceivers ? sonet/sdh transceivers and transponders ? fibre channel transceivers ? 10gbps transceivers ? free space optical communications ? proprietary optical links
micrel, inc. MIC3002 july 2007 2 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 or dering information part number package type junction temp. range package marking lead finish MIC3002bml 24- pin qfn ? 45c to +105c 3002 sn -pb MIC3002bmltr (1) 24- pin qfn ? 45c to +105c 3002 sn -pb MIC3002gml 24- pin qfn ? 45c to +105c 3002 with pb - free bar - line indicator pb - free nipdau MIC3002gmltr (1) 24- pin qfn ? 45c to +105c 3002 with pb - free bar - line indicator pb - free nipdau 1. note: 2. tape and reel.
micrel, inc. MIC3002 july 2007 3 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 contents pin configuration ............................................................................................................................................................. 7 pin description ................................................................................................................................................................ 7 absolute maximum ratings ............................................................................................................................................ 9 operating ratings ........................................................................................................................................................... 9 electrical characteristics ................................................................................................................................................. 9 timing diagram ............................................................................................................................................................. 14 address map ................................................................................................................................................................. 15 block diagram ............................................................................................................................................................... 18 analog - to - digital converter/signal monitoring .............................................................................................................. 18 temperature reading compensation ........................................................................................................................... 19 alarms and warnings interrupt source masking .......................................................................................................... 20 alarms and warnings as txfault source ................................................................................................................. 21 alarms and warnings latch .......................................................................................................................................... 21 s mbus multipart support .............................................................................................................................................. 21 calibration modes ......................................................................................................................................................... 22 a/ external calibration ............................................................................................................................................ 22 voltage .................................................................................................................................................................... 22 temperature ........................................................................................................................................................... 22 bi as current ............................................................................................................................................................ 22 tx power ................................................................................................................................................................ 22 rx power ................................................................................................................................................................ 23 b/ internal calibration ............................................................................................................................................. 23 temperature offset ................................................................................................................................................. 25 c/ adc result registers reading .......................................................................................................................... 25 rxpot ......................................................................................................................................................................... 25 laser diode bias control .............................................................................................................................................. 25 laser modulation control .............................................................................................................................................. 26 power on and laser start - up ...................................................................................................................................... 27 fault comparators ........................................................................................................................................................ 28 shdn and txfin .......................................................................................................................................................... 29 temperature measurement ........................................................................................................................................... 29 diode faults .................................................................................................................................................................. 29 temperature compensation ......................................................................................................................................... 29 alarms and warning flags ............................................................................................................................................ 32 control and status i/o ................................................................................................................................................... 32 system timing ............................................................................................................................................................... 34 warm resets ................................................................................................................................................................. 36 power - on hour meter ................................................................................................................................................... 36 test and calibration features ....................................................................................................................................... 37 serial port operation ..................................................................................................................................................... 38 page writes ................................................................................................................................................................... 38 acknowledge polling ....................................................................................................................................................... 39 write protection and data security .................................................................................................................................. 39 oem password ........................................................................................................................................................ 39 user password ......................................................................................................................................................... 39
micrel, inc. MIC3002 july 2007 4 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 detailed register descriptions ...................................................................................................................................... 40 alarm threshold registers ............................................................................................................................................ 40 warning threshold registers ........................................................................................................................................ 43 adc result registers ................................................................................................................................................... 45 alarm flags ................................................................................................................................................................... 48 warning flags ............................................................................................................................................................... 49 warning status register 0 (warn0) ............................................................................................................................ 49 warning status register 1 (warn1) ............................................................................................................................ 49 oem password entry (oempw) .................................................................................................................................. 5 0 user password setting (usrpwset) ....................................................................................................................... 50 user password (usrpw) ........................................................................................................................................... 51 power - on hours ........................................................................................................................................................... 51 data ready flags (datardy) ..................................................................................................................................... 51 user control register (usrctl) ............................................................................................................................... 52 oem configuration register 0 (oemcfg0) ................................................................................................................. 52 oem configuration register 1 (oemcfg1) ................................................................................................................. 53 oem configuration register 2 (oemcfg2) ................................................................................................................. 54 apc setpoint x ............................................................................................................................................................. 54 modulation setpoint x ................................................................................................................................................... 54 i bias fault threshold (ibflt) ......................................................................................................................................... 55 transmit power fault threshold (txflt) .................................................................................................................... 55 loss - of - signal threshold (losflt) ............................................................................................................................ 55 fault suppression timer (flttmr) ............................................................................................................................. 55 fault mask (fltmsk) ................................................................................................................................................... 56 oem password setting (oempwset) ........................................................................................................................ 56 oem calibration 0 (oemcal0) .................................................................................................................................... 57 oem calibration 1 (oemcal1) .................................................................................................................................... 57 oem calibration 1 (lut index) ..................................................................................................................................... 58 oem configuration 3 (oemcfg3) ............................................................................................................................... 58 bias dac setting (apcdac) current vbias setting .................................................................................................. 58 modulation dac setting (moddac) current vmod setting ....................................................................................... 59 oem readback register (oemrd) ............................................................................................................................. 59 signal detect threshold (losfltn) ............................................................................................................................. 59 rx eepot tap selection (rxpot) ............................................................................................................................. 60 oem configuration 4 (oemcfg4) ............................................................................................................................... 60 oem configuration 5 (oemcfg5) ............................................................................................................................... 61 oem configuration 6 (oemcfg6) ............................................................................................................................... 62 power - on hour meter data (pohdata) ..................................................................................................................... 62 oem scratchpad registers (sc ratchn) .................................................................................................................... 63 rx power look - up table (rxlutn) ............................................................................................................................. 63 calibration constants (caln) ....................................................................................................................................... 63 manufacturer id register .............................................................................................................................................. 64 device id register ....................................................................................................................................................... 64 package information ..................................................................................................................................................... 65
micrel, inc. MIC3002 july 2007 5 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 list of figures figure 1. MIC3002 block diagram ................................................................................................................................ 18 figure 2. analog - to - digital converter block diagram ................................................................................................... 18 figure 3. internal calibration rx power linear approximation .................................................................................... 25 figure 4. rxpot block diagram .................................................................................................................................. 25 figure 5. MIC3002 apc and modulation control block diagram ................................................................................ 26 figure 6. programmable feedback resistor ................................................................................................................ 26 figure 7. transmitter configurations supported by MIC3002 ..................................................................................... 26 figure 8. v mod configured as voltage output with gain .......................................................................................... 27 figure 9. MIC3002 power - on timing .......................................................................................................................... 28 figure 10. fault comparator logic ............................................................................................................................... 28 figure 11. saturation detector ...................................................................................................................................... 29 figure 12. rxlos comparator logic ........................................................................................................................... 29 figure 13. control and status i/o logic ........................................................................................................................ 33 figure 14. transmitter on - off timing ....................................................................................................................... 34 figure 15. initialization timing with txdisable asserted .......................................................................................... 34 figure 16. initialization timing with txdisable not asserted .................................................................................. 34 figure 17. loss - of - signal (los) timing ...................................................................................................................... 35 figure 18. transmit fault timing .................................................................................................................................. 28 figure 19. su ccessfully clearing a fault condition ..................................................................................................... 36 figure 20. unsuccessful attempt to clear a fault ....................................................................................................... 36 figure 21. write byte protocol ..................................................................................................................................... 38 figure 22. read byte protocol ..................................................................................................................................... 38 figure 23. read_word protocol ................................................................................................................................... 38 figure 24. four - byte page_white protocol ................................................................................................................. 39
micrel, inc. MIC3002 july 2007 6 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 list of tables table 1. MIC3002 address map, serial address = a0 h ................................................................................................ 15 table 2. MIC3002 address map, serial address = a2 h ................................................................................................ 15 table 3. temperature compensation tables, serial address = a4 h ............................................................................ 16 table 4. oem configuration re gisters, serial address = a6 h ...................................................................................... 17 table 5. a/d input signal ranges and resolutions ...................................................................................................... 19 table 6. v aux input signal ranges and resolutions .................................................................................................... 19 table 7. lut for temperature reading compensation ................................................................................................ 20 table 8. alarms interrupt sources masking bits ........................................................................................................... 20 table 9. warnings interrupt sources masking bits ....................................................................................................... 21 table 10. lsb values of offset coeffici ents ................................................................................................................. 23 table 11. internal calibration coefficient memory map ? part i ................................................................................... 24 table 12. internal calibration coefficient memory map ? part ii .................................................................................. 24 table 13. shutdown state of shdn vs. configuration bits ......................................................................................... 27 table 14. shutdown state of v bias vs. configuration bits ............................................................................................ 27 table 15. shutdown state of v mod vs. configuration bits ............................................................................................ 27 table 16. temperature compensation look - up tables ............................................................................................... 30 table 17. apc temperature compensation look - up table ....................................................................................... 31 table 18. v mod temperature compensation look - up table ....................................................................................... 31 table 19 . i bias comparator temperature compensation look - up table ..................................................................... 31 table 20. bias current high alarm temperature compensation table ...................................................................... 31 table 22. MIC3002 events ............................................................................................................................................ 33 table 23. power - on hour meter result format .......................................................................................................... 36 table 24. test and diagnostic features ...................................................................................................................... 37
micrel, inc. MIC3002 july 2007 7 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 pin configuration 24- pin qfn pin description pin number pin name pin function 1 fb analog input. feedback voltage for the apc loop op - amp. polarity and scale are programmable via the apc configuration bits. connect to v bias if apc is not used. 2 vmpd analog input. mult iplexed a/d converter input for monitoring transmitted optical power via a monitor photodiode. in most applications, vmpd will be connected directly to fb. the input range is 0 - v ref or 0 - v ref /4 depending on the setting of the apc configuration bits 3 gnda ground return for analog functions. 4 vdda power supply input for analog functions. 5 vild ? analog input. reference terminal for the multiplexed pseudo - differential a/d converter inputs for monitoring laser bias current via a sense resistor (vild+ i s the sensing input). tie to v dd or gnd to reference the voltage sensed on vild+ to v dd or gnd, respectively. limited common - mode voltage range, see ?applications information? section for more details. 6 vild+ analog input. multiplexed a/d input for monit oring laser bias current via a sense resistor (signal input); accommodates inputs referenced to v dd or gnd (see pin 5 description). limited common - mode voltage range, see ?applications information? section for more details. 7 shdn/txfin digital output/inp ut; programmable polarity. when used as shutdown output (shdn), oemcfg3 -2 set to 0, shdn is asserted at the detection of a fault condition if oemcfg4 - 7 is set to 0. if the latter bit is set to 1, a fault condition will not assert shdn. when programmed as t xfin, it is an input for external fault signals to be ored with the internal fault sources to drive txfault. 8 vrx analog input. multiplexed a/d converter input for monitoring received optical power. the input range is 0 to v ref . a 5 - bit programmable eepo t on this pin provides for coarse calibration and ranging of the rx power measurement. 9 xpn analog input/output. optional connection to an external pn junction for sensing temperature at a remote location. the zone bit in oemcfg1 determines whether tempe rature is measured using the on - chip sensor or the remote pn junction. 10 txfault digital output; open - drain, programmable polarity. if oemcfg5- 4 is set to 0, a high level indicates a hardware fault impeding transmitter operation. the state of this pin is always reflected in the txflt bit.
micrel, inc. MIC3002 july 2007 8 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 pin description pin number pin name pin function 11 txdisable digital input; active high. the transmitter is disabled when this line is high or the stxdis bit is set. the state of this input is always reflected in t he txdis bit. 12 data digital i/o; open - drain. bi - directional serial data input/output. 13 clk digital input; serial clock input. 14 vin/int if bit 4 (ie) in usrctl register is set to 0 (default), this pin is configured as analog input. if ie bit is set to 1, this pin is configured as open - drain output. analog input: multiplexed a/d input for monitoring supply voltage. 0v to 5.5v input range. open - drain output: outputs the internally generated interrupt signal /int. 15 rsin digital input; rate select i nput; ored with rate select bit to determine the state of the rsout pin. the state of this pin is always reflected in the rsel bit. 16 gndd ground return for digital functions. 17 nc no connection. this pin is used for test purposes and must be left unco nnected. 18 vddd power supply input for digital functions. 19 rxlos digital output; programmable polarity open - drain. indicates the loss of the received signal as indicated by a level of received optical power below the programmed rxlos comparator thresh old; may be wire - ored with external signals. normal operation is indicated by a low level when oemcfg6 - 3 is set to 0 and a high level when oemcfg6- 3 is set to 1. rxlos is de- asserted when vrx > losfltn. the los bit reflects the state of rxlos whether driv en by the MIC3002 or an external circuit. 20 rs0/gpo digital output. open - drain or push- pull. when used as rate select output, it represents the receiver rate select as per sff. this output is controlled by the srsel bit ored with rsin input and is open d rain only. when used as a general - purpose, non- volatile output, it is controlled by the gpo configuration bits in oemcfg3. 21 comp analog output, compensation terminal. connect a capacitor between this pin and gnda or v dda with appropriate value to tune t he apc loop time constant to a desirable value. 22 vbias analog output. buffered dac output capable of sourcing or sinking up to 10ma under control of the apc function to drive an external transistor for laser diode d.c. bias. the output and feedback pol arity are programmable to accommodate either a npn or a pnp transistor to drive a common - anode or common - cathode laser diode. 23 vmod ? analog input. inverting terminal of vmod buffer op - amp. connect to v mod + (gain = 1) or feedback resistors network to set a different gain 24 vmod+ analog output. buffered dac output to set the modulation current on the laser driver ic. operates with either a 0 ? v ref or a (v dd ? v ref ) ? v dd output swing so as to generate either a ground - referenced or a v dd referenced programm ed voltage. a simple external circuit can be used to generate a programmable current for those drivers that require a current rather than a voltage input. see ?applications information? section for more details.
micrel, inc. MIC3002 july 2007 9 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 absolute maximum ratings (1) power supply voltage, v dd ................................. +3.8v voltage on clk, data, txfault, vin, rxlos, disable, rsin ..................................? 0.3v to +6.0v voltage on any other pin ............... ? 0.3v to v dd +0.3v power dissipation, t a = 85c ............................... 1.5w junction temperature (t j ) .................................. 150c storage temperature (t s ) ................. ? 65c to +150c esd ratings (3) human body model ............................................. 2kv machine model .................................................. 300v soldering (20sec) ................................................. 260oc operating ratings (2) power supply voltage, v dda /v ddd ..... +3.0v to +3.6v ambient temperature range (t a ) ... ? 40c to +105c package th ermal resistance qfn ( ja ) ............................................... 43c/w electrical characteristics for typical values, t a = 25c, v dda = v ddd = +3.3v, unless otherwise noted. bold values are guaranteed for +3.0v (v dda = v ddd ) 3.6v, t (min) t a t (max) (8) symbol parameter condition m in typ max units power supply i dd supply current clk = data = v ddd = v dda ; txdisable low; all dacs at full - scale; all a/d inputs at full - scale; all other pins open. 2.3 3.5 ma clk = data = v ddd = v dda ; txdisable high; fltdac at full - scale; all a/d i nputs at full - scale; all other pins open. 2.3 3.5 ma v por power - on reset voltage all registers reset to default values; a/d conversions initiated. 2.9 2.98 v v uvlo under - voltage lockout threshold note 5 2.5 2.73 v v hyst power - on reset hysteresis volt age 170 mv t por power - on reset time v dd > v por (4) 50 s v ref reference voltage 1.210 1.225 1.240 v ? v ref / ? v dda voltage reference line regulation 1.7 mv/v temperature -to - digital converter characteristics local temperature measurement error ? 4 0c t a +105c (6) 1 3 c remote temperature measurement error ? 40c t a +105c (6) 1 3 c t conv conversion time note 4 60 ms t sample sample period 100 ms remote temperature input, xpn i f current to external diode (4) xpn at high level, clamped to 0.6v. 192 400 a xpn at low level, clamped to 0.6v. 7 12 a
micrel, inc. MIC3002 july 2007 10 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 voltage -to - digital converter characteristics (v rx , v aux , v bias , v mpd , v ild ) symbol parameter condition min typ max units voltage measurement error ? 40c t a +105c (6) 1 2.0 %fs t conv conversion time note 4 10 ms t sample sample period note 4 100 ms voltage input, v in (pin 14 used as an adc input) v in input voltage range ? 0.3 v dd 3.6v gnda 5.5 v i leak input current v in = v dd or gnd; v aux = v in 55 a c in nput capacitance 10 pf digital -to - voltage converter characteristics (v mod , v bias ) accuracy ? 40c t a +105c (6) 1 2.0 %fs t conv conversion time note 4 20 ms dnl differential non - linearity error note 4 0.5 1 lsb bias current sense inputs, v ild +, v ild ? v ild differential input signal range, | v ild + ? v ild ? | 0 v ref /4 mv i in+ v ild + input current 1 a i in ? v ild ? input current | v ild + ? v ild ? | = 0.3v v ild ? referred to v dda +150 a v ild ? referred to gnd -150 a c in input capac itance 10 pf apc op amp, fb, v bias , comp gbw gain bandwidth product c comp = 20pf; gain = 1 1 mhz tc vos input offset voltage temperature coefficient (4) 1 v/c v out output voltage swing i out = 10ma, srce bit = 1 gnda 1.25 v i out = - 10ma, src e bit = 0 v dda - 1.25 v dda v i sc output short - circuit current 55 ma t sc short circuit withstand time t j 150c (4) sec psrr power supply rejection ratio c comp = 20pf; gain = 1, to gnd 55 db c comp = 20pf; gain = 1, to v dd 40 a min minimum s table gain c comp = 20pf, note 4 1 v/v ? v/ ? t slew rate c comp = 20pf; gain = 1 3 v/s ? rfb internal feedback resistor tolerance 20 % ? rfb/ ? t internal feedback resistor temperature coefficient 25 ppm/c i start laser start - up current magnitude st art = 01 h 0.375 ma start = 02 h 0.750 ma start = 04 h 1.500 ma start = 08 h 3.000 ma c in pin capacitance 10 pf
micrel, inc. MIC3002 july 2007 11 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 electrical characteristics symbol parameter condition min typ max units v mod buffer op - amp, v mod +, v mod ? gbw gain bandwidth c comp = 20pf; gain = 1 1 mhz tc vos input offset voltage temperature coefficient 1 v/c i bias v mod ? input current 0.1 1 a v out output voltage swing i out = 1ma gnda+75 v dda -75 mv i sc output short - circuit current 35 ma t sc short circuit w ithstand time t j 150c (4) sec psrr power supply rejection ratio c comp = 20pf; gain = 1, to gnd 65 db c comp = 20pf; gain = 1, to v dd 44 db a min minimum stable gain c comp = 20pf 1 v/v ? v/ ? t slew rate c comp = 20pf; gain = 1 1 v/s c in pin capacitance 10 pf control and status i/o, txdisable, txfault, rsin, rsout(gpo), shdn(txfin), rxlos, /int v il low input voltage 0.8 v v ih high input voltage 2.0 v v ol low output voltage i ol 3ma 0.3 v v oh high output voltage (applies to shd n only) i oh 3ma v ddd ? 0.3 v i leak input current 1 a c in input capacitance 10 pf transmit optical power input, v mpd v in input voltage range note 4 gnda v dda v v rx input signal range biasref=0 v ref v biasref=1 v dda ? v ref v dda v c in inp ut capacitance note 4 10 pf i leak input current 1 a received optical power input, vrx, rxpot input voltage range note 4 gnda v dda v v rx valid input signal range (adc input range) 0 v ref v r rxpot(32) end -to - end resistance rxpot = 1f h 32 k? ? rxpot resistor tolerance 20 % ? rxpot/ ? t resistor temperature coefficient 25 ppm/c ? v rx /v rxpot divider ratio accuracy 00 rxpot 1f h -5 +5 % i leak input current rxpot = 0 (disconnected) 1 a c in input capacitance note 4 10 pf i leak in put current 1 a
micrel, inc. MIC3002 july 2007 12 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 electrical characteristics symbol parameter condition min typ max units control and status i/o timing, txfault, txdisable, rsin, rsout, and rxlos t off txdisable assert time from input asserted to optical output at 10% of nominal, c comp = 10nf. 10 s t on txdisable de - assert time from input de - asserted to optical output at 90% of nominal, c comp = 10nf. 1 ms t init initialization time from power on or transmitter enabled to optical output at 90% of nominal and tx_fault de - asserted. (4) 300 ms t init2 power - on initialization time from power on to apc loop - enabled. 200 ms t fault txfault assert time from fault condition to txfault assertion. (4) 95 s t reset fault reset time length of time txdisable must be asserted to reset fau lt condition. 10 s t loss_on rxlos assert time from loss of signal to rxlos asserted. 95 s t loss_off rxlos de - assert time from signal acquisition to los de - asserted. 100 s t data analog parameter data ready from power on to valid analog parameter data available. (4) 400 ms t prop_in txfault, txdisable, rxlos, rsin input propagation time time from input change to corresponding internal register bit set or cleared. (4) 1 s t prop_out txfault, rsout, /int output propagation time from an internal r egister bit set or cleared to corresponding output change. (4) 1 s fault comparators flttmr fault suppression timer clock period note 4 0.475 0.5 0.525 ms accuracy -3 +3 %/f.s. t reject glitch rejection maximum length pulse that will not cause output to change state. (4) 4.5 s v sat saturation detection threshold high level 95 %vd da low level 5 %vdda power - on hour meter timebase accuracy 0c t a +70c (4) +5 -5 % ? 40c t a +105c +10 -10 % resolution note 4 10 hours non - volatile (flash) memory t wr write cycle time(7) from stop of a one to four - byte writ e transaction.(4) 13 ms data retention 100 years endurance minimum permitted number write cycles 10,000 cycles
micrel, inc. MIC3002 july 2007 13 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 serial data i/o pin, data symbol parameter condition min typ max units v ol low output voltage i ol = 3ma 0.4 v i ol = 6ma 0.6 v v il low input voltage 0.8 v v ih high input voltage 2.1 v i leak input current 1 a c in input capacitance note 4 10 pf serial clock input, clk v il low input voltage 2. 7v v dd 3.6v 0.8 v v ih high input voltage 2.7v v dd 3.6v 2.1 v i leak input current 1 a c in input capacitance note 4 10 pf serial interface timing (4) t 1 clk (clock) period 2.5 s t 2 data in setup time to clk high 100 ns t 3 data out stable after clk low 300 ns t 4 data low setup time to clk low start condition 100 ns t 5 data high hold time after clk high stop condition 100 ns t data data ready time from power on to completion of one set of adc conversions; analog data ava ilable via serial interface. 400 ms notes: 1. exceeding the absolute maximum rating may damage the device. 2. the device is not guaranteed to function outside its operating rating. 3. devices are esd sensitive. handling precautions recommended. 4. guaranteed by de signing and/or testing of related parameters. not 100% tested in production. 5. the mic3000 will attempt to enter its shutdown state when v dd falls below v uvlo . this operation requires time to complete. if the supply voltage falls too rapidly, the operation m ay not be completed. 6. does not include quantization error. 7. the MIC3002 will not respond to serial bus transactions during an eeprom write - cycle. the host will receive a nack during t wr . 8. final test on outgoing product is performed at t a = +25c.
micrel, inc. MIC3002 july 2007 14 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 timing diag ram serial interface timing
micrel, inc. MIC3002 july 2007 15 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 address map address(s) field size (bytes) name description 0 ? 95 96 serial id defined by sep msa g - p nvram; r/w under valid oem password. 96 ? 127 32 vendor specific vendor specific eeprom 128 ? 255 128 reserved reserved for future use. g - p nvram; r/w under valid oem password. table 1. MIC3002 address map, serial address = a0 h address(s) field size (bytes) hex dec name description 00-27 0 -39 40 alarm and warning threshold high/low limits for warning and alarms; writ eable using oem p/w; read - only otherwise. 28-37 40-55 16 reserved reserved ? do not write; reads undefined. 38-5b 56-91 36 calibration constants numerical constants for external calibration; writeable using oem p/w; read - only otherwise. 5c -5e 92-94 3 re served reserved ? do not write; reads undefined. 5f 95 1 checksum g - p nvram; writeable using oem p/w; ready only otherwise. 60-69 96- 105 10 analog data real time analog parameter data. 6a -6d 106- 109 4 reserved reserved ? do not write; reads undefined. 6e 110 1 control/status bits control and status bits. 6f 111 1 reserved reserved ? do not write; reads undefined. 70-71 112- 113 2 alarm flags alarm status bits; read only. 72-73 114- 115 2 reserved reserved ? do not write; reads undefined. 74-75 116- 117 2 warning flags warning status bits; read only. 76-77 118- 119 2 reserved reserved ? do not write; reads undefined. 78-7e 120- 126 7 oempw oem password entry field. the oem password location can be selected to be 78 - 7b (120- 123) or 7b - 7e (123 - 126) by sett ing the bit oemcfg5 bit 2 to 0 (default) or 1. 7f 127 1 vendor specific vendor specific. reserved ? do not write; reads undefined. 80-dd 128- 221 94 user scratchpad user writeable eeprom. g - p nvram; r/w using any valid password. de 222 1 alt_usrctl alter nate location for usrctl register. set bit oemcfg6 - 2 to 1 to select this location. can be used as a scratch pad if not selected. df - f5 223- 245 23 user scratchpad user writeable eeprom. g - p nvram; r/w using any valid password. f6 246 1 usrpwset user passw ord setting; read/write using any p/w; returns zero otherwise. f7 247 1 usrpw user password register f8 - f9 248- 249 2 alarms masks bit =1: corresponding alarm not masked bit = 0: corresponding alarm masked fa - fb 250- 251 2 warnings masks bit =1: correspon ding warning not masked bit = 0: corresponding warning masked fc - fe 252- 254 3 reserved reserved ? do not write; reads undefined. ff 255 1 usrctl end - user control and status bits if alt - usrctl is not selected. can be used as a scratch pad if not selected. table 2. MIC3002 address map, serial address = a2 h
micrel, inc. MIC3002 july 2007 16 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 address(s) field size (bytes) hex dec name description 00-3f 0 -63 64 biaslut1 bias temperature compensation l.u.t. first 64 entries. additional 12 entries are located in a6: 90 - 9b. 40-7f 64- 127 64 modlut1 modulation temperature compensation l.u.t. first 64 entries. additional 12 entries are located in a6: a0 -ab. 80-bf 128- 191 64 iftlut1 bias current fault threshold temperature compensation l.u.t. first 64 entries. additional 12 entries are located in a6: b0 - bb. c0 - ff 192- 255 64 hatlut1 bias current high alarm threshold temperature compensation l.u.t. first 64 entries. additional 12 entries are located in a6: c0 - cb. table 3. temperature compensation tables, serial address = a4 h address(s) field si ze (bytes) hex dec name description 00 0 1 oemcfg0 oem configuration register 0 01 1 1 oemcfg1 oem configuration register 1 02 2 1 oemcfg2 oem configuration register 2 03 3 1 apcset0 apc setpoint register 0 04 4 1 apcset1 apc setpoint register 1 05 5 1 apcset2 apc setpoint register 2 06 6 1 modset0 modulation setpoint register 0 07 7 1 ibflt bias current fault - comparator threshold. this register is temperature compensated 08 8 1 txpflt tx power fault threshold 09 9 1 losflt rx los fault - compar ator threshold 0a 10 1 flttmr fault comparator timer setting 0b 11 1 fltmsk fault source mask bits 0c -0f 12-15 4 oempwset password for access to oem areas 10 16 1 oemcal0 oem calibration register 0 11 17 1 oemcal1 oem calibration register 1 12 18 1 l utindx look - up table index read - back 13 19 1 oemcfg3 oem configuration register 3 14 20 1 apcdac reads back current apc dac value (setpoint+offset) 15 21 1 moddac reads back current modulation dac value (setpoint+offset) 16 22 1 oemread reads back oem calibration data 17 23 1 losfltn los de - assert threshold 18 24 1 rxpot rxpot tap selection 19 25 1 oemcfg4 oem configuration register 4 1a 26 1 oemcfg5 oem configuration register 5 1b 27 1 oemcfg6 oem configuration register 6 1c -1d 28-29 2 scratch re served ? do not write; reads undefined. 1e 30 1 modset 1 modulation setpoint register 1 1f 31 1 modset 2 modulation setpoint register 2
micrel, inc. MIC3002 july 2007 17 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 20-27 32-39 8 pohdata power - on hour meter scratchpad 28-47 40-71 32 rxlut rx power calibration look - up table. eight sets of slope and offset 48-57 72-87 16 calcoef slope and offset coefficients used for temperature, voltage, bias, and txpower internal calibration 58-5f 88-95 8 scratch oem scratchpad area 60-86 96-134 39 tctrlut lut to temperature - compensate temperatu re results and/or temperature to be used by parameters compensation lut. 87-8f 135- 143 9 scratch oem scratchpad area. 90-9b 144- 155 12 biaslut2 bias temperature compensation l.u.t. additional 12 entries. 9c -9f 156- 159 4 scratch oem scratchpad area a0 -ab 160- 171 12 modlut2 modulation temperature compensation l.u.t. additional 12 entries. ac -af 172- 175 14 scratch oem scratchpad area. b0 -bb 176- 187 12 iftlut2 bias current fault threshold temperature compensation l.u.t. additional 12 entries. bc -bf 188- 191 4 scratch oem scratchpad area c0 -cb 192- 203 12 hatlut2 bias current high alarm threshold temperature compensation l.u.t. additional 12 entries. cc-cf 204- 207 4 scratch oem scratchpad area d0 -dd 208- 221 14 rxlutseg rxpwr calibration segments delimit ers. each of the eight segments can have its own slope and offset. de - fa 222- 250 128 scratch oem scratchpad area fb - fc 251- 252 2 poh power on hour meter result; read only fd 253 1 data ready flags data ready bits for each measured parameter; read only fe 254 1 mfg_id manufacturer identification (micrel = 42 = 2ah) ff 255 1 dev_id device and die revision table 4. oem configuration registers, serial address = a6 h
micrel, inc. MIC3002 july 2007 18 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 block diagram figure 1. MIC3002 block diagram analog - to - digital converter/signal monitor ing a block diagram of the monitoring circuit is shown below. each of the five analog parameters monitored by the MIC3002 are sampled in sequence. all five parameters are sampled and the results updated within the t conv internal given in the ?electrical ch aracteristics? section. in oem , mode, the channel that is normally used to measure v in may be assigned to measure the level of the v dda pin or one of five other nodes. this provides a kind of analog loopback for debug and test purposes. the v aux bits in oe mcfg0 control which voltage source is being sampled. the various v aux channels are level - shifted differently depending on the signal source, resulting in different lsb values and signal ranges. see table 5. figure 2. analog -to - digital converter block dia gram
micrel, inc. MIC3002 july 2007 19 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 channel adc resolution (bits) conditions input range (v) lsb (1) temp 8 or 9 n/a 1c or 0.5c vaux 8 see table 6 vmpd 8 gain = 0; biasref = 0 gnda - v ref 4.77mv gain = 0; biasref = 1 v dda ? (v dda ? v ref ) gain = 1; biasref = 0 gnda - v ref / 4 1.17mv gain = 1; biasref = 1 v dda ? (v dda ? v ref /4 ) vild 8 vild - = vdda v dda ? (v dda ? v ref ) 4.77mv vild - = gnda gnda - v ref vrx 12 rxpot = 00 0 - v ref 0.298mv table 5. a/d input signal ranges and resolutions note: 1. assumes typical vref value o f 1.22v. channel vaux [2:0] input range (v) lsb (1) (mv) v in 000 = 00 h 0.5v to 5.5v 25.6mv v dda 0001 = 01 h 0.5v to 5.5v 25.6mv v bias 010 = 02 h 0.5v to 5.5v 25.6mv v mod 011 = 03 h 0.5v to 5.5v 25.6mv apcdac 100 = 04 h 0v to v ref 4.77mv moddac 101 = 05 h 0v to v ref 4.77mv fltdac 110 = 06 h 0v to v ref 4.77mv table 6. v aux input signal ranges and resolutions note: 1. assumes typical v ref value of 1.22v. temperature reading compensation the sensed temperature by the MIC3002 can be temperature compensate d and converted to the optical module case temperature to be monitored or used for modulation and other parameters (l.u.t.s). there are 39 entries (bytes) at address a6: 96 - 134 (60 - 86h) where the oem can enter the temperature difference between the chip (s ensed) temperature and the measured module case temperature over the operating temperature range. table 7 shows the correspondence between the entries and temperature intervals. the resolution of this table is 0.5oc/bit. the number entered should be twice the temperature difference. for example if the chip - case temperature difference is 5oc, the value to be entered should be 2x5=10.
micrel, inc. MIC3002 july 2007 20 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 entry address temperature range 0 a6: 96 (60h) t - 45 oc 1 a6: 97 (61h) - 44 oc t - 41 oc 2 a6: 98 (62h) - 40 oc t - 37 oc ??????????????????????????????? ??????????????????????????????? 36 a6: 97 (61h) 96 oc t 99 oc 37 a6: 97 (61h) 100 t 103 oc 38 a6: 134 (86h) t 104 oc table 7. l.u.t. for temperature reading compensation alarms and warnings interrupt source masking alarms and warnings set the flags and interrupt when they are asserted if they are not masked (default). if an alarm or warni ng is masked, it will not set the interrupt. table 8 shows the locations of the masking bits. the warning or alarm is masked if the corresponding bit is set to 1. serial address a2h default value description byte bit 248 7 0 masking bit for temp high alarm interrupt source 6 0 masking bit for temp low alarm interrupt source 5 0 masking bit for voltage high alarm interrupt source 4 0 masking bit for voltage low alarm interrupt source 3 0 masking bit for bias high alarm interrupt source 2 0 masking bit for bias low alarm interrupt source 1 0 masking bit for tx power high alarm interrupt source 0 0 masking bit for tx power low alarm interrupt source 249 7 0 masking bit for rx power high alarm interrupt source 6 1 masking bit for r x power low alarm interrupt source 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 reserved table 8. alarms interrupt sources masking bits
micrel, inc. MIC3002 july 2007 21 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 serial address a2h default value description byte bit 250 7 0 masking bit f or temp high warning interrupt source 6 0 masking bit for temp low warning interrupt source 5 0 masking bit for voltage high warning interrupt source 4 0 masking bit for voltage low warning interrupt source 3 0 masking bit for bias high warning int errupt source 2 0 masking bit for bias low warning interrupt source 1 0 masking bit for tx power high warning interrupt source 0 0 masking bit for tx power low warning interrupt source 251 7 0 masking bit for rx power high warning interrupt sourc e 6 1 masking bit for rx power low warning interrupt source 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 reserved table 9. warnings interrupt sources masking bits alarms and warnings as txfault source alarms and warnings are not sources for txfault with the default setting. to set alarms as a txfault source set oemcfg4 bit 6 to 1. to set warnings as a txfault, source set oemcfg4 bit 7 to 1. the alarms and warnings txfault sources can be masked individually in the same way shown in tables 7 and 8. alarms and warnings latch alarms and warnings are latched with the default setting, i.e., the flags once asserted remain on until the register is read or txdsable is toggled. if oemcfg4 bit 5 is set to 1, the warnings are not latc hed and will be set and reset with the warning condition. reading the register or toggling txdisable will clear the flag. if oemcfg4 bit 4 is set to 1, the alarms are not latched and will be set and reset with the alarm condition. reading the register or t oggling txdisable will clear the flag. smbus multipart support if more than one MIC3002 device shares the same serial interface and multipart mode is selected on them (oemcfg5 bit 3 = 1), then pin 7 and pin 20 become smbus address bits 3 and 4 respectivel y. therefore, the parts should have a different setting on those pins to create four address combinations based upon pin 7 and pin 20 state, (00, 01, 10, 11) where 0 is a pull down to gnd and 1 is a pull up to vcc. the parts come from the factory with the same address (a0) and multipart mode off (oemcfg5 bit 3 = 0). after power up, write 1 to oemcfg5 bit 3 to turn on multipart mode, which is done to all parts at the same time since they all respond to serial address a0 at this point. with multipart mode on , the parts have different addresses based on the states of pins 7 and 20. another option is to access each part individually, set their single mode address in oemcfg2 bits [4 - 7] to different values and then turn off multipart mode to return to normal mode where the parts have new different address.
micrel, inc. MIC3002 july 2007 22 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 calibration modes the default mode of calibration in the MIC3002 is external calibration, for which intcal bit (bit 0 in oemcf3 register) is set to 0. the internal calibration mode is selected by setting i ntcal bit to 1. a/ external calibration the voltage and temperature values returned by the MIC3002?s a/d converter are internally calibrated. the binary values of temph:templ and volth:voltl are in the format called for by sff - 8472 under internal calibrat ion. sff - 8472 calls for a set of calibration constants to be stored by the transceiver oem at specific non - volatile memory locations; refer to sff - 8472 specifications for memory map of calibration coefficient. the MIC3002 provides the non - volatile memory r equired for the storage of these constants. the digital diagnostic monitoring interface specification should be consulted for full details. slopes and offsets are stored for use with voltage, temperature, bias current, and transmitted power measurements. c oefficients for a fourth - order polynomial are provided for use with received power measurements. the host system can retrieve these constants and use them to process the measured data. voltage the voltage values returned by the MIC3002?s a/d converter are internally calibrated. the binary values of volth:voltl are in the format called for by sff - 8472 under internal calibration. since vinh:vinl requires no processing, the corresponding slope should be set to one and the offset to zero. temperature the tempe rature values returned by the MIC3002?s a/d converter are internally calibrated. the binary values of temph:templ are in the format called for by sff - 8472 under internal calibration. bias current bias current is sensed via an external sense resistor as a v oltage appearing between vild+ and vild - . the value returned by the a/d is therefore a voltage analogous to bias current. bias current, ibias, is simply v vild /r sense . the binary value in ibiash (ibiasl is always zero) is related to bias current by: (1 ) the value of the least significant bit (lsb) of ibiash is given by: (2) per sff - 8472, the value of the bias current lsb is 2a. the conversion factor, ?slope?, needed is therefore: the tolerance of the sense resistor directly impacts the a ccuracy of the bias current measurement. it is recommended that the sense resistor chosen be 1% accurate or better. the offset correction, if needed, can be determined by shutting down the laser, i.e., asserting txdisable, and measuring the bias current. a ny non - zero result gives the offset required. the offset will be equal and opposite to the result of the ?zero current? measurement. tx power transmit power is sensed via a resistor carrying the monitor photodiode current. in most applications, the signal at vmpd will be feedback voltage on fb. the vmpd voltage may be measured relative to gnd or v dda depending on the setting of the biasref bit in oemcfg1. the value returned by the a/d is therefore a voltage analogous to transmit power. the binary value in t xoph (txopl is always zero) is related to transmit power by: (3) for a given implementation, the value of r sense is known. it is either the value of the external resistor or the chosen value of rfb used in the application. the constant, k, will likely ha ve to be determined through experimentation or closed - loop calibration, as it depends on the monitoring photodiode responsivity and coupling efficiency. it should be noted that the apc circuit acts to hold the transmitted power constant. the value of trans mit power reported by the circuit should only vary by a small amount as long as apc is functioning correctly.
micrel, inc. MIC3002 july 2007 23 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 rx power received power is sensed as a voltage appearing at vrx. it is assumed that this voltage is generated by a sense resistor carrying the r eceiver photodiode current or by the rssi circuit of the receiver. the value returned by the a/d is therefore a voltage analogous to received power. the binary values in rxoph and rxopl are related to receive power by: rx(mw) = k x vref x (256 x rxoph +rx opl/16)/ 65536 (4) for a given implementation, the constant, k, will likely have to be determined through experimentation or closed - loop calibration, as it depends upon the gain and efficiencies of the receiver. in sff - 8472 implementations, the externa l calibration constants can describe up to a fourth - order polynomial in case k is nonlinear. b/ internal calibration if the intcal bit in oemcfg3 is set to 1 (internal calibration selected), the MIC3002 will process each piece of data coming out of the a/d converter before storing the result in memory. linear slope/offset correction will be applied on a per - channel basis to the measured values for voltage, bias current, tx power, and rx power. only compensation is applied to temperature. the user must store the appropriate slope/offset parameters in memory at the time of transceiver calibration. in the case of rx power, a look - up table is provided that implements eight - segment piecewise - linear correction. this correction may be performed as a compensation of the receiver non - linearity over receive power level. if static slope/offset correction for rx power is desired, the eight coefficient sets can simply be made the same. the memory maps for these coefficients are shown in tables 11 and 12. the user must ent er the seven delimiters of the intervals that fit better the receiver response. the diagram in figure 3 shows the link between the delimiters and the sets of slopes/offsets. the slopes allow for the correction of gain errors. each slope coefficient is an u nsigned, sixteen - bit, fixed - point binary number in the format: [mmmmmmmm.llllllll] , where m is a data bit (5) in the most - significant byte and l is a data bit in the least significant byte slopes are always positive. the binary point is in between the two bytes, i.e., between bits 7 and 8. this provides a numerical range of 1/256 (0.00391) to 255.997 in steps of 1/256. the most significant byte is always stored in memory at the lower numerical address. the offsets correct for constant errors in the mea sured data. each offset is a signed, sixteen - bit, fixed - point binary number. the bit - weights of the offsets are the same as that of the final results. the sixteen - bit offsets provide a numerical range of ? 32768 to +32767 for voltage, bias current, transmit power, and receive power. the numerical range for the temperature offset is ? 32513 ( ? 128) to +32512 (+127) in increments of 256 (1). the format for offsets is: [smmmmmmmllllllll] , where s is the sign bit (6) (0 = positive, 1 = negative), m is a dat a bit in the most - significant byte and l is a data bit in the least significant byte the most significant byte is always stored in memory at the lower numerical address. calibration of voltage, bias current, and tx power are performed using the followi ng calculation: resultn = adc_resultn x slopen + (7) offsetn calibration of rx power is performed using the following calculation: result = adc_result x slope(m) + (9) offset(m) where m represents one of the eight linearization intervals cor responding to the rx power level. the results of these calculations are rounded to sixteen bits in length. if the seventeenth most significant bit is a one, the result is rounded up to the next higher value. if the seventeenth most significant bit is zero, the upper sixteen bits remain unchanged. the bit - weights of the offsets are the same as that of the final results. for sff - 8472 compatible applications, these bit - weights are given in table 10. parameter magnitude of lsb voltage 100v bias current 2a tx power 0.1w rx power 0.1w table 10. lsb values of offset coefficients
micrel, inc. MIC3002 july 2007 24 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 address(s) field size hex dec name description 48-49 72-73 2 reserved reserved. (there is no slope for temperature.) do not write; reads undefined. 4a -4b 74-75 2 reserved reserved. (there is no offset for temperature.) do not write; reads undefined. 4c -4d 76-77 2 vslph:vslpl voltage slope; unsigned fixed - point; msb is at lower physical address. 4e -4f 78-79 2 voffh:voffl voltage offset; signed fixed point; msb is at lower physical address. 50-51 80-81 2 islph:islpl bias current slope; unsigned fixed - point; msb is at lower physical address. 52-53 82-83 2 ioffh:ioffl bias current offset; signed fixed point; msb is at lower physical address. 54-55 84-85 2 txslph: txslpl tx power slope; unsigned fixed - point; msb is at lower physical address. 56-57 86-87 2 txoffh: txoffl tx power offset; signed fixed point; msb is at lower physical address. table 11. internal calibration coefficient memory map ? part i address(s) field siz e hex dec name description 28-29 40-41 2 rxslp0h: rxslp0l rx power slope 0; unsigned fixed - point; msb is at lower physical address. 2a -2b 42-43 2 rxoff0h: rxoff0l rx power offset 0; signed twos - complement; msb is at lower physical address. 2c -2d 44-45 2 rxslp1h: rxslp1l rx power slope 1; unsigned fixed - point; msb is at lower physical address. 2e -2f 46-47 2 rxoff1h: rxoff1l rx power offset 1; signed twos - complement; msb is at lower physical address. 30-31 48-49 2 rxslp2h: rxslp2l rx power slope 2; u nsigned fixed - point; msb is at lower physical address. 32-33 50-51 2 rxoff2h: rxoff2l rx power offset 2; signed twos - complement; msb is at lower physical address. 34-35 52-53 2 rxslp3h: rxslp3l rx power slope 3; unsigned fixed - point; msb is at lower phys ical address. 36-37 54-55 2 rxoff3h: rxoff3l rx power offset 3; signed twos - complement; msb is at lower physical address. 38-39 56-57 2 rxslp4h: rxslp4l rx power slope 4; unsigned fixed - point; msb is at lower physical address. 3a -3b 58-59 2 rxoff4h: rxo ff4l rx power offset 4; signed twos - complement; msb is at lower physical address. 3c -3d 60-61 2 rxslp5h: rxslp5l rx power slope 5; unsigned fixed - point; msb is at lower physical address. 3e -3f 62-63 2 rxoff5h: rxoff5l rx power offset 5; signed twos - compl ement; msb is at lower physical address. 40-41 64-65 2 rxslp6h: rxslp6l rx power slope 6; unsigned fixed - point; msb is at lower physical address. 42-43 66-67 2 rxoff6h: rxoff6l rx power offset 6; signed twos - complement; msb is at lower physical address. 44-45 68-69 2 rxslp7h: rxslp7l rx power slope 7; signed twos - complement; msb is at lower physical address. 46- 47 70- 71 2 rxoff7h: rxoff7l rx power offset 7; signed fixed - point; msb is at lower physical address. table 12. internal calibration coefficien t memory map ? part ii
micrel, inc. MIC3002 july 2007 25 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 figure 3. internal calibration rx power linear approximation temperature offset in both internal and external calibration, the temperature offset is set in the temperature reading compensation lut (see subsection above). bit 5 in omcfg5 (a6:1ah) must be set to 1 in order to enable temperature reading compensation. since the resolution of that l.u.t. is 0.5oc, the entered value should be twice the real value. for example, if the content of the l.u.t. is 0 for all the entries and th e offset is 5oc, then the offset value to be added to the entries content is 10. the new content of the l.u.t. entries will be 0+10=10. c/ adc result registers reading the adc result registers should be read as 16 - bit registers under internal calibration while under external calibration they should be read as 8 - bit or 16 - bit registers at the msb address. for example, tx power should be read under internal calibration as 16 bits at address a2 h : 66 ? 67 and under external calibration as 8 bits at address a2 h : 66 h . 9 - bit temperature results and 12 - bit receive power results should always be read as 16 - bit quantities. rxpot a programmable, non - volatile digitally controlled potentiometer is provided for adjusting th e gain of the receive power measurement signal chain in the analog domain. five bits in the rxpot register are used to set and adjust the position of potentiometer. rxpot functions as a programmable divider or attenuator. it is adjustable in steps from 1:1 (no divider action) down to 1/32 in steps of 1/32. if rxpot is set to zero, then the divider is bypassed completely. there will be no scaling of the input signal, and the resistor network will be disconnected from the vrx pin. at all other settings of rxp ot, there will be a 32k ? (typical) load seen on vrx. figure 4. rxpot block diagram laser diode bias control the MIC3002 can be configured to generate a constant bias current using electrical feedback, or regulate average tr ansmitted optical power using a feedback signal from a monitor photodiode, refer to figure 5. an operational amplifier is used to control laser bias current via the v bias output. the vbias pin can drive a maximum of 10ma. an external bipolar transistor pr ovides current gain. the polarity of the op amp?s output is programmable biasref in oemcfg1 in order to accommodate either npn or pnp transistors that drive common anode and common cathode laser, respectively. additionally, the polarity of the feedback sig nal is programmable for use with either common - emitter or emitter - follower transistor circuits.
micrel, inc. MIC3002 july 2007 26 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 furthermore, the reference level for the apc circuit is selectable to accommodate electrical, i.e., current feedback, or optical feedback via a monitor photod iode. finally, any one of seven different internal feedback resistors can be selected. this internal resistor can be used alone or in parallel with an external resistor. this wide range of adjustability (50:1) accommodates a wide range of photodiode curren t, i.e., wide range of transmitter output power. the apc operating point can be kept near the mid - scale value of the apc dac, insuring maximum snr, maximum effective resolution for digital diagnostics, and the widest possible dac adjustment range for tempe rature compensation, etc. see figure 6. the apccal bit in oemcal0 is used to turn the apc function on and off. it will be turned off in the MIC3002?s default state as shipped from the factory. when apc is on, the value in the selected apcsetx register is added to the signed value taken from the apc look - up table and loaded into the v bias dac. when apc is off, the v bias dac may be written directly via the v bias register, bypassing the look - up table entirely. this provides direct control of the laser diode b ias during setup and calibration. in either case, the v bias dac setting is reported in the apcdac register. the apccfg bits determine the dacs response to higher or lower numeric values. figure 5. MIC3002 apc and modulation control block diagram figure 6. programmable feedback resistor laser modulation control as shown in figure 5, a temperature - compensated dac is provided to set and control the laser modulation current via an external laser driver circuit. modref in oemcfg0 selects whether the v mod dac output swings up from ground or down from v dd . if the laser driver requires a voltage input to set the modula tion current, the MIC3002?s v mod output can drive it directly. if a current input is required, a fixed resistor can be used between the driver and the v mod output. several different configurations are possible as shown in figure 8. when apc is on, i.e., th e apccal bit in oemcal0 is set to 0, the value corresponding to the current temperature is taken from the modlut look - up table, added to modset, and loaded into the v mod dac. when apc is off, the value in v mod is loaded directly into the v mod dac, bypassin g the look - up table entirely. this provides for direct modulation control for setup and calibration. the modref bit determines the dacs response to higher or lower numeric values. figure 7. transmitter configurations supported by MIC3002
micrel, inc. MIC3002 july 2007 27 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 figure 8. v mod configured as voltage output with gain power on and l aser start - up when power is applied, then the MIC3002 initializes its internal registers and state machine. this process takes t por , about 50ms. following t por , analog - to - digital conversions begin, serial communication is possible, and the por bit and data ready bits may be polled. the first set of analog data will be available t conv after t por . MIC3002s are shipped from the factory with the output enable bit, oe, set to zero, off. the MIC3002?s power - up default state, ther efore, is apc off, v bias , v mod , and shdn outputs disabled. v bias , v mod , and shdn will be floating (high impedance) and the laser diode, if connected, will be off. once the device is incorporated into a transceiver and properly configured, then the shutdown states of shdn, v bias and v mod will be determined by the state of the apc configuration and oe bits. tables 13, 14, and 15 illustrate the shutdown states of the various laser control outputs versus the control bits. configuration bits shutdown state oe spol shdn 0 don?t care hi -z 1 0 gnd 1 1 v dd table 13. shutdown state of shdn vs. configuration bits configuration bits v bias shutdown state oe inv biasref v bias 0 don?t care don?t care hi -z 1 don?t care 0 gnd 1 don?t care 1 v dd table 14. shut down state of v bias vs. configuration bits configuration bits v mod shutdown state oe modref v mod 0 don?t care hi -z 1 0 gnd 1 1 v dd table 15. shutdown state of v mod vs. configuration bits in order to facilitate hot - plugging, the laser diode is not turned on until t init2 after power - on. following t init2 , and assuming txdisable is not asserted, the dacs will be loaded with their initial values. since t conv is much less than t init2 , the first set of analog data, including temperature, is available at t init2 . temperature compensation will be applied to the dac values if enabled. apc will begin if oe is asserted. (if the output enable bit, oe, is not set, the v mod , v bias , and shdn outputs will float indefinitely.) figure 9 shows the power - up timing of the MIC3002. if txdisable is asserted at power - up, the v mod and v bias outputs will stay in their shutdown states following MIC3002 initialization. a/d conversions will begin, but the laser will remain off.
micrel, inc. MIC3002 july 2007 28 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 figure 9. MIC3002 power - on timing (oe = 1) fault comparators in addition to detecting and reporting the events specified in sff - 8472, the MIC3002 also monitors five fault conditions: inadequate supply voltage, thermal diode faults, excessive bias current, excessive transmit power, and apc op - amp s aturation. comparators monitor these parameters in order to respond quickly to fault conditions that could indicate link failure or safety issues, see figure 10. when a fault is detected, the laser is shut down and txfault is asserted. each fault source ma y be independently disabled using the fltmsk register. fltmsk is non - volatile, allowing faults to be masked only during calibration and testing or permanently. figure 10. fault comparator logic thermal diode faults are detected within the temperature me asurement subsystem when an out - of - range signal is detected. a window comparator circuit monitors the voltage on the compensation capacitor to detect apc op - amp saturation (figure 11). op - amp saturation indicates that some fault has occurred in the control loop such as loss of feedback. the saturation detector is blanked for a time, tflttmr, following laser turn - on since the compensation voltage will essentially be zero at turn - on. the flttmr interval is programmable from 0.5ms to 127ms (typical) in increm ents of 0.5ms (tflttmr). note that a saturation comparator cannot be relied upon to meet certain eye - safety standards that require 100ms response times. this is because the operation of a saturation detector is limited by the loop bandwidth, i.e., the choi ce of c comp . even if the comparator itself was very fast, it would be subject to the limited slew - rate of the apc op - amp. only the other fault comparator channels will meet <100ms timing requirements. the MIC3002 can also except and respond to fault input s from external devices. see ?shdn and txfin? section. a similar comparator circuit monitors received signal strength and asserts rxlos when loss - of - signal is detected (figure 12). rxlos will be asserted when and if vrx drops below the level programmed in losflt. hysteresis is implemented such that rxlos will be de - asserted when vrx subsequently rises above the level programmed in losfltn. the loss - of - signal comparator may be disabled completely by setting the losdis bit in oemcfg3. once the los comparator is disabled, an external device may drive rxlos. the state of the rxlos pin is reported in the cntrl register regardless of whether it is driven by the internal comparator or by an external device. a programmable digital - to - analog converter provides the co mparator reference voltages for monitoring
micrel, inc. MIC3002 july 2007 29 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 received signal strength, transmit power, and bias current. glitches less than 10ms (typical) in length are rejected by the fault comparators. since laser bias current varies greatly with temperature, there is a t emperature compensation look - up table for the bias current fault dac value. when a fault condition is detected, the laser will be shutdown immediately and txfault will be asserted. the v mod , v bias , and shdn if enabled, oemcfg5 - 7 is set to 1, outputs will be driven to their shutdown state according to the state of the configuration bits. the shutdown states of v mod , v bias , and shdn versus the configuration bit settings are shown in table 13, table 14, and table 15. shdn and txfin shdn and txfin are optional functions of pin 7. shdn is an output function and is designed to drive a redundant safety switch in the laser current path. txfin is an input function and serves as an input for fault signals from external devices that must be reported to the host via tx fault. the shdn function is designed for applications in which the MIC3002 is performing all apc and laser management tasks. the txfin function is for situations in which an external device such as a laser diode driver ic is performing laser management tas ks, including fault detection. if the txfin bit in oemcfg3 is zero (the default mode), shdn will be activated anytime the laser is off. thus, it will be active if 1) txdisable is asserted, 2) stxdis in cntrl, is set, or 3) a fault is detected. shdn is a pu sh - pull logic output. its polarity is programmable via the spol bit in oemcfg1. if txfin is set to one, pin 7 serves as an input that accepts fault signals from external devices such as laser diode driver ics. multiple txfault signals cannot simply be wire - ored together as they are open - drain and active high. the input polarity is programmable via the txfpol bit in oemcfg3. txfin is logically ored with the MIC3002?s internal fault sources to produce txfault and determine the value of the transmit fault bit in cntrl. see figure 10. figure 11. saturation detector figure 12. rxlos comparator logic temperature measurement the temperature - to - digital converter for both internal and external temperature data is built around a switched current source and an eig ht - bit/nine - bit analog - to - digital converter. the temperature is calculated by measuring the forward voltage of a diode junction at two different bias current levels. an internal multiplexer directs the current source?s output to either an internal or exter nal diode junction. the value of the zone bit in oemcfg1 determines whether readings are taken from the on - chip sensor or from the xpn input. the external pn junction may be embedded in an integrated circuit, or it may be a diode - connected discrete transis tor. this data is also used as the input to the temperature compensation look - up tables. each time temperature is sampled and an updated value acquired, new corrective values for imod and the apc setpoint are read from the corresponding tables, added to th e set values, and transferred to the dacs. diode faults the MIC3002 is designed to respond in a failsafe manner to hardware faults in the temperature sensing circuitry. if the connection to the sensing diode is lost or the sense line is shorted to v dd or g round, the temperature data reported by the a/d converter will be forced to its full - scale value (+127c). the diode fault flag, dflt, will be set in oemcfg1, txfault will be asserted, and the high temperature alarm and warning flags will be set. the repor ted temperature will remain +127c until the fault condition is cleared. diode faults may be reset by toggling txdisable, as with any other fault. diode faults will not be detected at power up until the first a/d conversion cycle is completed. diode faults are not reported while txdisable is asserted. temperature compensation since the performance characteristics of laser diodes and photodiodes change with operating temperature, the
micrel, inc. MIC3002 july 2007 30 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 MIC3002 provides a facility for temperature compensation of the a.p.c. loop set - point, laser modulation current, bias current fault comparator threshold, and bias current high alarm flag threshold. temperature compensation is performed using a look - up table (lut) that stores values corresponding to each measured temperature over a 150c span. four identical tables reside at serial address a4h and a6h as summarized in table 16. each table entry is a signed twos complement number that is used as an offset to the parameter being compensated. the default value of all table entries is zero, giving a flat response. the a/d converter reports a new temperature sample each t conv . this occurs at roughly 10hz. to prevent temperature oscillation due to thermal or electrical noise, sixteen successive temperature samples are averaged together an d used to index the l.u.t.s. temperature compensation results are therefore. updated at 16xt conv intervals, or about 1.6 seconds. this can be expressed as shown in equation 10: (10) each time an updated average value is acquired, a new offset value for the apc setpoint is read from the corresponding look - up table (see table 17) and transferred to the apc circuitry. this is illustrated in equation 11. in a same way, new offset values are taken from similar look - up tables (see table 18 and table 19), added to the nominal values and transferred into the modulation and fault comparator dacs. the bias current high alarm threshold is compensated using a fourth look - up table (see table 20). this compensation happens internally and does not affect any host - access ible registers. (11) if the measured temperature is greater than the maximum table value, the highest value in each table is used. if the measured temperature is less than the minimum, the minimum value is used. hysteresis is employed to further e nhance noise immunity and prevent oscillation about a table threshold. each table entry spans two degrees c. the table index will not change unless the new temperature average results in a table index beyond the midpoint of the next entry in either directi on. there is therefore 2 to 3c of hysteresis on temperature compensation changes. the table index will never oscillate due to quantization noise as the hysteresis is much larger than 1 ?2 lsb. serial address byte addresses function i2cadr+4h 00h? 3fh apc look - up table 40h? 7fh i mod look - up table 80h? bfh iflt look - up table c0h ? ffh bias high alarm look - up table i2cadr+6h 90h? 9bh apc look - up table (cont.) a0h ? abh i mod look - up table (cont.) b0h ? bbh iflt look - up table (cont.) c0h ? cbh bias high alarm look - up table (cont.) table 16. temperature compensation look - up tables
micrel, inc. MIC3002 july 2007 31 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 seri al address register address table offset temperature offset (c) i2cadr+4h 00h 0 -45 01h 1 -44 -43 ? ? ? ? ? ? ? ? ? 3fh 63 80 81 i2cadr+6h 90h 64 82 83 ? ? ? ? ? ? 9a 74 102 103 9b 75 104 table 17. apc temperature compensation look - up table serial address register address tab le offset temperature offset (c) i2cadr+4h 40h 0 -45 41h 1 -44 -43 ? ? ? ? ? ? ? ? ? 7fh 63 80 81 i2cadr+6h a0 64 82 83 ? ? ? ? ? ? aa 74 102 103 ab 75 104 table 18. v mod temperature compensatio n look - up table serial address register address table offset temperature offset (c) i2cadr+4h 80h -45 81h -44 -43 82h ? ? ? 8eh 8fh 63 80 81 i2cadr+6h b0 64 82 83 ? ? ? ? ? ? ba 74 102 103 bb 75 104 table 19. i bias comparator temperature compensation look - up table serial address register address table offset temperature offset (c) i2cadr+4h c0h -45 c1h -44 -43 c2h ? ? ? feh ffh 63 80 81 i2cadr+6 h c0 64 82 83 ? ? ? ? ? ? ca 74 102 103 table 20. bias current high alarm temperature compensation table
micrel, inc. MIC3002 july 2007 32 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 the internal state machine calculates a new table index each time a new average temperature value becomes available. this table index is derived from the average temperature value. the table index is then converted into a table address for each of the four look - up tables. these operations can be expressed as: (12) where tavg(n) is the current average temperature; and table_address=in dex+base_addres where base_address is the physical base address of each table, i.e., 00 h , 40 h , 80 h , or c0 h (tables reside in the i2cadr+4h and i2cadr+6h pages of memory). at any given time, the current table index can be read in the lutindx register. alar ms and warning flags there are 20 different conditions that will cause the MIC3002 to set one of the bits in the warnx or alarmx registers. these conditions are listed in table 22. the less critical of these events generate w arning flags by setting a bit in warn0 or warn1. the more critical events cause bits to be set in alarm0 or alarm1. an event occurs when any alarm or warning condition becomes true. each event causes its corresponding status bit in alarm0, alarm1, warn0, or warn1 to be set. this action cannot be masked by the host. the status bit will remain set until the host reads that particular status register, a power on - off cycle occurs, or the host toggles txdisable. if txdisable is asserted at any time during norma l operation, a/d conversions continue. the a/d results for all parameters will continue to be reported. all events will be reported in the normal way. if they have not already been individually cleared by read operations, when txdisable is de - asserted, all status registers will be cleared. control and status i/o the logic for the transceiver control and status i/o is shown schematically in figure 13. note that the internal drivers on rxlos, rate_select, and txfault are all open - drain. these signals may be driven either by the internal logic or external drivers connected to the corresponding MIC3002 pins. in any case, the signal level appearing at the pins of the MIC3002 will be reported in the control register status bits. note that the control bits for tx_disable and rate_select and the status bits for txfault and rxlos do not meet the timing requirements as specified in the sfp msa or the gbic specification, revision 5.5 (sff - 8053) for the hardware signals. the speed of the ser ial interface limits the rate at which these functions can be manipulated and/or reported. the response time for the control and status bits is given in the ?electrical characteristics? subsection.
micrel, inc. MIC3002 july 2007 33 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 event condition MIC3002 response tempera ture high alarm temp > tmax set alarm0[7] temperature low alarm temp < tmin set alarm0[6] voltage high alarm vin > vmax set alarm0[5] voltage low alarm vin < vmin set alarm0[4] tx bias high alarm ibias > ibmax set alarm0[3] tx bias low alarm ibias < i bmin set alarm0[2] tx power high alarm txop > txmax set alarm0[1] tx power low alarm txop < txmin set alarm0[0] rx power high alarm rxop > rxmax set alarm1[7] rx power low alarm rxop < rxmin set alarm1[6] temperature high warning temp > thigh set warn 0[7] temperature low warning temp < tlow set warn0[6] voltage high warning vin > vhigh set warn0[5] voltage low warning vin < vlow set warn0[4] tx bias high warning ibias > ibhigh set warn0[3] tx bias low warning ibias < iblow set warn0[2] tx power h igh warning txop > txhigh set warn0[1] tx power low warning txop < txlow set warn0[0] rx power high warning rxop > rxhigh set warn1[7] rx power low warning rxop < rxlow set warn1[6] table 22. MIC3002 events figure 13. control and status i/o logic
micrel, inc. MIC3002 july 2007 34 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 system timing the timing specifications for MIC3002 control and status i/o are given in the ?electrical characteristics? subsection. figure 14. transmitter on - off timing figure 15. initialization timing with txdisable ass erted figure 16. initialization timing with txdisable not asserted
micrel, inc. MIC3002 july 2007 35 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 figure 17. loss - of - signal (los) timing figure 18. transmit fault timing
micrel, inc. MIC3002 july 2007 36 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 figure 19. successfully clearing a fault condition figure 20. unsuccessful attempt to clear a fault warm resets the MIC3002 can be reset to its power - on default state during operation by setting the reset bit in oemcfg0. when this bit is set, txfault and rxlos will be de - asserted, all registers will be restored to their norm al power - on default values, and any a/d conversion in progress will be halted and the results discarded. the state of the MIC3002 following this operation is indistinguishable from a power - on reset. power - on hour meter the power - o n hour meter logs operating hours using an internal real - time clock and stores the result in nvram. the hour count is incremented at ten - hour intervals in the middle of each interval. the first increment therefore takes place five hours after power - on. tim e is accumulated whenever the MIC3002 is powered. the hour meter?s time base is accurate to 5% over all MIC3002 operating conditions. the counter is capable of storing counts of more than thirty years, but is ultimately limited by the write - cycle endurance of the non - volatile memory. this implies a range of at least twenty years. actual results will depend upon the operating conditions and write - cycle endurance of the part in question. two registers, pohh and pohl, contain a 15 - bit power - on hour measurement and an error flag, pohflt. great care has been taken to make the MIC3002?s hour meter immune to data corruption and to insure that valid data is maintained across power cycles. the hour meter employs multiple data copies and error correction codes to main tain data validity. this data is stored in the pohdata registers. if pohflt is set, however, the power - on hour meter data has been corrupted and should be ignored. it is recommended that a two - byte (or more) sequential read operation be performed on pohh and pohl to insure coherency between the two registers. these registers are accessible by the oem using a valid oem password. the only operation that should be performed on these registers is to clear the hour meters initial value, if necessary, at the tim e of product shipment. the hour meter result may be cleared by setting all eight pohdata bytes to 00 h . power - on hour result format high byte, pohh low byte, pohi error flag elapsed time / 10 hours, msbs elapsed time / 10 hours, lsbs msb lsb table 23. power - on hour meter result format
micrel, inc. MIC3002 july 2007 37 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 test and calibration features numerous features are included in the MIC3002 to facilitate development, testing, and diagnostics. these features are available via registers in the oe m area. as shown in table 24, these features include: function description control register(s) analog loop - back provides analog visibility of op - amp and dac outputs via the adc oemcfg0 fault comparator disable control disables the fault comparator oemcal0 fault comparator spin -on- channel mode selects a single fault comparator channel oemcal0 fault comparator output read - back allows host to read individual fault comparator outputs oemrd rsout, /int read - back allows host to read the state of these pins oemrd inhibit eeprom write cycles speeds repetitive writes to registers backed up by nvram oemcal0 apc calibration mode allows direct writes to moddac and apcdac (temperature compensation not used) oemcal0 continuity checking forcing of rxlos, txfa ult, /int oemcal0 halt a/d stops a/d conversions; adc in one - shot mode oemcal1 adc idle flag indicates adc status oemcal1 a/d one - shot mode performs a single a/d conversion on the selected input channel oemcal1 a/d spin -on- channel mode selects a singl e input channel oemcal1 channel selection selects adc or fault comparator channel for spin -on - channel modes oemcal1 lut index read - back permits visibility of the lut index calculated by the state - machine lutindx manufacturer and device id registers faci litates presence detection and version control mfg_id, dev_id table 24. test and diagnostic features
micrel, inc. MIC3002 july 2007 38 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 serial port operation the MIC3002 uses standard write_byte, read_byte, and read_word operations for communication with its host. it also supports page_write and sequential_read transactions. the write_byte operation involves sending the device?s slave address (with the r/w bit low to signal a write operation), followed by the address of the register to be operated upon and the data byte. the read_byte operation is a composite write and read operation: the host first sends the device?s slave address followed by the register address, as in a write operation. a new start bit must then be sent to the MIC3002, followed by a repeat o f the slave address with the r/w bit (lsb) set to the high (read) state. the data to be read from the part may then be clocked out. a read_word is similar, but two successive data bytes are clocked out rather than one. these protocols are shown in figures 21 to 24. the MIC3002 will respond to up to four sequential slave addresses depending upon whether it is in oem or user mode. a match between one of the MIC3002?s addresses and the address specified in the serial bit stream must be made to initiate communi cation. the MIC3002 responds to slave addresses a0 h and a2 h in user mode; it also responds to a4 h and a6 h in oem mode (assuming i2cadr = ax h ). page writes to increase the speed of multi - byte writes, the MIC3002 allows up to four consecut ive bytes (one page) to be written before the internal write cycle begins. the entire non - volatile memory array is organized into four - byte pages. each page begins on a register address boundary where the last two bits of the address are 00 b . thus, the pa ge is composed of any four consecutive bytes having the addresses xxxxxx00 b , xxxxxx01 b , xxxxxx10 b , and xxxxxx11 b . the page write sequence begins just like a write_byte operation with the host sending the slave address, r/w bit low, register address, etc. a fter the first byte is sent the host should receive an acknowledge. up to three more bytes can be sent in sequence. the MIC3002 will acknowledge each one and increment its internal address register in anticipation of the next byte. after the last byte is s ent, the host issues a stop. the MIC3002?s internal write process then begins. if more than four bytes are sent, the MIC3002?s internal address counter wraps around to the beginning of the four - byte page. to accelerate calibration and testing, nvram write cycles can be disabled completely by setting the wrinh bit in oemcal0. writes to registers that do not have nvram backup, will not incur write - cycle delays when writes are inhibited. write operations on registers that exist only in nvram will still incur w rite cycle delays. figure 21. write byte protocol figure 22. read byte protocol figure 23. read_word protocol
micrel, inc. MIC3002 july 2007 39 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 figure 24. four - byte page white protocol acknowledge polling the MIC3002?s non - volatile memory cannot be accessed during the internal write process. to allow for maximum speed bulk writes, the MIC3002 supports acknowledge polling. the MIC3002 will not acknowledge serial bus transactions while internal writes are in progress. the host may therefore monitor for the end of the write process by periodically checking for an acknowledgement. write protection and data security oem password a password is required to access the oem areas of the MIC3002, specifically the non - volatile memory, look - up tables, and registers at serial addresses a4 h and a6 h . a four - byte field, oempwset, at serial address a6 h is used for setting the oem password. the oem password is set by writing oempwset with the new value. the password comparison is performed following the write to the msb of the oempw, address 7b h (or 7e h ) at serial address a2 h . therefore, this byte must be written last. a four - byte burst - write sequence to address 78 h (or 7b h ) may be used as this will result in the msb being writ ten last. the new password will not take effect until after a power - on reset occurs or a warm reset is performed using the rst bit in oemcfg0. this allows the new password to be verified before it takes effect. the corresponding four - byte field for passwo rd entry, oempw, is located at serial address a2 h . this field is therefore always visible to the host system. oempw is compared to the four - byte oempwset field at serial address a6 h . if the two fields match, access is allowed to the oem areas of the mic300 2 non - volatile memory at serial addresses a4 h and a6 h . if oempwset is all zeroes, no password security will exist. the value in oempw will be ignored. this helps prevent a deliberately unsecured MIC3002 from being inadvertently locked. once a valid passwor d is entered, the MIC3002 oem areas will be accessible. the oem areas may be re - secured by writing an incorrect password value at oempw, e.g., all zeroes. in all cases, oempw must be written lsb first through msb last. the oem areas will be inaccessible fo llowing the final write operation to oempw?s lsb. the oempw field is reset to all zeros at power on. any values written to these locations will be readable by the host regardless of the locked/unlocked status of the device. if oempwset is set to zero (0000 0000 h ), the MIC3002 will remain unlocked regardless of the contents of the oempw field. this is the factory default security setting. note that a valid oem password allows access to the oem and user areas of the chip, i.e., the entire memory map, regardle ss of any user password that may be in place. once the oem areas are locked, the user password can provide access and write protection for the user areas. user password a password is required to access the user areas of the MIC3002, spe cifically, the non - volatile memory at serial addresses a0 h and a2 h . a one - byte field, usrpwset at serial address a2 h is used for setting the user password. usrpwset is compared to the usrpw field at serial address a2 h . if the two fields match, access is al lowed to the user areas of the MIC3002 non - volatile memory at serial addresses a0 h and a2 h . the user password is set by writing usrpwset with the new value. the new password will not take effect until after a power - on reset occurs or a warm reset is perfor med using the rst bit in oemcfg0. this allows the new password to be verified before it takes effect. note also that a valid oem password allows access to the oem and user areas of the chip, i.e., the entire memory map, regardless of any user password tha t may be in place. once the oem areas are locked, the user password can then provide access and write protection for the user areas. if a valid oem password is in place, the user password will have no effect.
micrel, inc. MIC3002 july 2007 40 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 detailed register descriptions note: serial bus addresses shown assume that i2cadr = ax h . alarm threshold registers temperature high alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0c) serial address a2 h byte address msb (txmahh): 00 = 00 h lsb (txmahl): 00 = 01 h each lsb of tmaxh represents one degree centigrade. this register is to be used in conjunction with tmaxl to yield a si xteen - bit temperature value. the value in this register is uncalibrated. the nine msbits of threshold value (tmaxh;tmaxl) are compared bit to bit to the nine msbits value of the temperature reading (temph;templ).. alarm bit ax is set if reading > threshol d. temperature low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0c) serial address a2 h byte address msb (tminh): 02 = 02 h lsb (tminl): 02 = 02 h each lsb of tminh represents one degree centigrade. tminh is to be used in conjunction with tminl to yield a sixteen - bit temperature value. the value in this register is uncalibrated. the nine ms bits of threshold value (tminh;tminl) are compared, bit to bit, to the nine msbits value of the temperature reading (temph;templ). alarm bit ax is set if reading < threshold. voltage high alarm threshold d[7] read/write d[6] read/write d[5] read/writ e d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0v) serial address a2 h bytes address msb (vmaxh): 08 = 08 h lsb (vmaxl): 09 = 09 h each lsb of vmaxh represents 25.6mv and each lsb of vmax l represents 0.1mv. the sixteen bits threshold value (vmaxh;vmaxl) is compared bit to bit to the sixteen bits value of the voltage reading (vinh;vinl). alarm bit ax is set if rea ding > threshold.
micrel, inc. MIC3002 july 2007 41 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 voltage low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0v) serial address a2 h bytes address msb (vminh): 10 = 0a h lsb (vminl): 11 = 0b h each lsb of vminh represe nts 25.6mv and each lsb of vminl represents 0.1mv. the sixteen bits threshold value (vminh;vminl) is compared bit to bit to the sixteen bits value of the voltage reading (vinh;vinl). alarm bit ax is set if rea ding < threshold. bias current high alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0ma) serial address a2 h bytes address msb (imaxh): 16 = 10 h lsb (imaxl): 17 = 1 1 h each lsb of imaxh represents 512 a and each lsb of imaxl represents 2 a. the sixteen bits threshold value (imaxh;imaxl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ildh:ildl). alarm bit ax is set if reading > thresho ld. bias current low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0ma) serial address a2 h byte address msb (iminh): 18 = 12 h lsb (iminl): 19 = 13 h each lsb of iminh represents 512 a and each lsb of iminl represents 2 a. the sixteen bits threshold value (iminh;iminl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ildh:ildl). alarm bit ax is set if reading < thr eshold. tx optical power high alarm d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0mw) serial address a2 h byte address msb (txmaxh): 24 = 18 h lsb (txmaxl): 25 = 19 h 24 = 18 h each lsb of txmaxh represents 25.6 w. this register is to be used in conjunction with txmaxl to yield a sixteen - bit value. the values in txmaxh:txmaxl are in an unsigned binary format. the value in this register is uncalibrated. the sixteen bits threshold value (txmaxh;txmaxl) is compared, bit to bit, to the sixteen bits value of the tx power reading (txoph:txopl). alarm bit ax is set if reading > threshold.
micrel, inc. MIC3002 july 2007 42 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 tx optical power low alarm d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0mw) serial address a2 h byte address msb (txmaxh): 24 = 18 h lsb (txmaxl): 25 = 19 h each lsb of txminh represents 25.6 w. this register is to be used in conjunction with txminl to yield a sixteen - bit value. the values in txminh:tminl are in an unsigned binary format. the value in this register is uncalibrated. the sixteen bits threshold value (txminh;txminl) is compared, bit to bit, to the sixteen bits value of the rtx power reading (txoph:txopl). alarm bit ax is set if reading < threshold. rx optical power high alarm threshold msb (rxmaxh) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/writ e d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0mw) serial address a2 h bytes address msb (rxmaxh): 32 = 20 h lsb (rxmaxl): 33 = 21 h each lsb of rxmaxh represents 25.6 w. this register is to be used in conjunction with rxmaxl to yield a sixteen - bit value. the value in this register is uncalibrated. the sixteen bits threshold value (rxmaxh;rxmaxl) is compared, bit to bit, to the sixteen bits value of the rx power reading (rxoph:rxopl). alarm bit ax is set if reading > threshold. rx optical power low alarm threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0mw) serial address a2 h byte address msb (rxminh): 34 = 22 h lsb (rxminl): 35 = 23 h each lsb of rxminh represents 25.6 w. this register is to be used in conjunction with rxminl to yield a sixteen - bit value. the value in this register is uncalibrated. the sixteen bits threshold value (rxminh;rxminl) is compared, bit to bit, to the sixteen bits value of the rx power reading (rxoph:rxopl). alarm bit ax is set if reading < threshold.
micrel, inc. MIC3002 july 2007 43 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 warning threshold registers temperature high warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read /write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0c) serial address a2 h bytes address msb (thighh): 04 = 04 h lsb (thighl): 05 = 05 h each lsb of thighh represents one degree centigrade. this register is to be used in conjunction with thighl to yield a sixteen - bit temperature value. the value in this register is uncalibrated. the nine msbits of threshold value (thighh;thighl) are compared, bit to bit, to the nine msbits value of the temperature reading (temph;templ).. warning bit wx is set if reading > threshold. temperature low warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0c) serial address a2 h bytes address msb (tlowh): 06 = 06 h lsb (tlowl): 06 = 06 h each lsb of tlowh represents one degree centigrade. this register is to be used in conjunction with tlowl to yield a sixteen - bit temperature value. the value in this register is uncalibrated . the threshold value (thighh;thighl) is compared, bit to bit, to the value of the temperature reading (temph;templ). warning bit wx is set if reading < threshold, voltage high warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] re ad/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0v) serial address a2 h bytes address msb (vhighh): 12 = 0c h lsb (vhighl): 13 = 0d h 12 = 0c h each lsb of vhighh represents 25.6mv. this register is to be used in conjunction with vhighl to yield a sixteen - bit value. the value in this register is uncalibrated. the threshold value (vhighh;vhighl) is compared. bit to bit. to the value of the voltage reading (vinh;vinl). warning bit wx is set if reading > threshold. voltage low warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0v) serial address a2 h byte address msb (vl owh): 14 = 0e h lsb (vlowl): 15 = 0f h each lsb of vlowh represents 25.6mv. this register is to be used in conjunction with vlowl to yield a sixteen - bit value. the value in this register is uncalibrated. the threshold value (vlowh;vlowl) is compared. bit t o bit, to the value of the voltage reading (vinh;vinl). warning bit wx is set if reading < threshold.
micrel, inc. MIC3002 july 2007 44 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 bias current high warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/wri te d[0] read/write default value 0000 0000 b = 00 h (0ma) serial address a2 h bytes address msb (ihighh): 20 = 14 h lsb (ihighl): 21 = 15 h each lsb of ihighh represents 512 a and each lsb of ihighl represents 2 a. the sixteen bits threshold value (ihighh;ihighl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ildh:ildl). warning bit wx is set if reading > threshold. bias current low warnin g threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0ma) serial address a2 h bytes address msb (ilowh): 22 = 16 h lsb (ilowl): 23 = 1 7 h each lsb of ilowh represents 512 a and each lsb of ilowl represents 2 a. the sixteen bits threshold value (ilowh;ilowl) is compared, bit to bit, to the sixteen bits value of the bias current reading (ildh:ildl). warning bit wx is s et if reading < threshold. tx optical power high warn ing msb (txhighh) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0mw) serial address a2 h bytes address msb (txhighh): 28 = 1c h lsb (txhigh l): 29 = 1d h each lsb of txhighh represents 25.6 w. this register is to be used in conjunction with txhighl to yield a sixteen - bit value. the values in txhighh:txhighl are in an unsigned binary format. the value in this register is uncalibrated. the sixteen bits threshold value (txhighh;txhighl) is comp ared, bit to bit, to the sixteen bits value of the tx power reading (txoph:txopl). warning bit wx is set if reading > threshold. tx optical power low warning d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/w rite d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0mw) serial address a2 h byte address msb (txlowh): 30 = 1e h lsb (txlowl): 31 = 1f h each lsb of txlowh represents 25.6 w. this register is to be used in conjunction with txlowl to yield a sixteen - bit value. the values in txlowh:tlowl are in an unsigned binary format. the value in this register is uncalibrated. the sixteen bits threshold value (txlowh;txlowl) is compared, bit to bit, to the sixteen bits value of the tx power reading (txoph:txopl). warning bit wx is set if reading < threshold.
micrel, inc. MIC3002 july 2007 45 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 rx optical power high warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] r ead/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0mw) serial address a2 h byte address msb (rxhighh): 36 = 24 h lsb (rxhighl): 37 = 25 h each lsb of rxhighh represents 25.6 w and each ach lsb of rxhighl represents 0.1 w.. the value in this register is uncalibrated. the sixteen bits threshold value (rxhighh;rxhighl) is compared, bit to bit, to the sixteen bits value of the rx power reading (rxoph:rxopl). warning bit wx is set if reading > threshold. rx optical power low warning threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0mw) serial address a2 h byte address 38 = 26 h each lsb of rxlowh represents 25.6 w and each eah lsb of rxlowl represents 0.1 w. the value in this register is uncalibrated. the sixteen bits threshold value (rxlowh;rxlowl) is compared, bit to bit, to the sixteen bits value of the rx power reading (rxoph:rxopl). warning bit wx is set if reading > threshold. checksum (chksum) checksum of bytes 0 - 94 at serial address a2h d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h (0c ) serial address a2 h byte address 95 = 5f h this register is provided for compliance with sff - 8472. it is implemented as general - purpose non- volatile memory. read/write access is possible whenever a valid oem password has been entered. chksum is read - on ly in user mode. adc result registers temperature result d[7] read - only d[6] read - only d[5] read - only d[4] read - only d[3] read - only d[2] read - only d[1] read - only d[0] read - only default value 0000 0000 b = 00 h (0c) (1) serial address a2 h byte address msb (temph): 96 = 60 h lsb (templ): 97 = 61 h each lsb of temph represents one degree centigrade. the temph register is to be used in conjunction with templ to yield a sixteen - bit temperature value. if oemcfg6 bit 1 is a zero, temperature is read t o 1c resolution in temph only, and templ is zero. if oemcfg6 bit 1 is a one, then temperature is read to 0.5c resolution as a nine - bit value consisting of temph and the ms bit of templ. the lower seven bits of templ are zero.
micrel, inc. MIC3002 july 2007 46 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 voltage d[7] read - onl y d[6] read - only d[5] read - only d[4] read - only d[3] read - only d[2] read - only d[1] read - only d[0] read - only default value 0000 0000 b = 00 h (0v) (2) serial address a2 h byte address msb (vinh): 98 = 62 h lsb (vinl): 99 = 63 h each lsb of vinh represe nts 25.6mv. vinh register is to be used in conjunction with vinl to yield a sixteen - bit value. the values in vinh:vlnl are in an unsigned binary format. the value in this register is uncalibrated. the host should process the results using the scale factor and offset provided. see the external calibration section. in the MIC3002, vinl will always return zero. it is provided for compliance with sff - 8472. notes: 1. temph will contain measured temperature data after the completion of one conversion. 2. vinh w ill contain measured data after one a/d conversion cycle. laser diode bias current d[7] read - only d[6] read - only d[5] read - only d[4] read - only d[3] read - only d[2] read - only d[1] read - only d[0] read - only default value 0000 0000 b = 00 h (0ma) (3) serial address a2 h byte address msb (ildh):100 = 64 h lsb (ildl):100 = 65 h ildh is to be used in conjunction with ildl to yield a sixteen - bit value. the values in ildh:ildl are in an unsigned binary format. the value in this register is uncalibrated. th e host should process the results using the scale factor and offset provided. see the external calibration sections. in the MIC3002, ildl will always return zero. it is provided for compliance with sff - 8472. transmitted optical power d[7] read - only d[6] read - only d[5] read - only d[4] read - only d[3] read - only d[2] read - only d[1] read - only d[0] read - only default value 0000 0000 b = 00 h (0mw) (5) serial address a2 h byte address msb (txoph): 102 = 66 h lsb (txopl): 103 = 67 h each lsb of txoph rep resents 25.6 w. thoph is to be used in conjunction with txopl to yield a sixteen - bit value. the values in txoph:txopl are in an unsigned binary format. the value in this register is uncalibrated. the host should process the results using the scale factor a nd offset provided. see the external calibration section. in the MIC3002, this txopl will always return zero. it is provided for compliance with sff - 8472. notes: 3. ildh will contain measured data after one a/d conversion cycle. 4. the scale factor cor responding to the sense resistor used must be set in the configuration register. 5. txoph will contain measured data after one a/d conversion cycle.
micrel, inc. MIC3002 july 2007 47 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 received optical power d[7] read - only d[6] read - only d[5] read - only d[4] read - only d[3] read - only d[2] read - only d[1] read - only d[0] read - only default value 0000 0000 b = 00 h (0mw) (6) serial address a2 h byte address msb (rxoph): 104 = 68 h lsb (rxopl): 105 = 69 h each lsb of rxopl represents 25.6 w and each lsb of rxopl represents 0.1 w. rxoph is to be used in conjunction with rxopl to yield a sixteen - bit value. the values in rxoph:rxopl are in an unsigned binary format. the value in this register is uncalibrated. the host should process the results using the scale factor and offset provided. see t he external calibration section. control and status (cntrl) d[7] txdis read - only d[6] stxdis read/write d[5] reserved d[4] rsel read/write d[3] srsel read/write d[2] xflt read - only d[1] los read - only d[0] por read - only default value 0000 0000 b = 00 h serial address a2 h byte address 110 = 6e h bit(s) function operation d[7] txdis reflects the state of the txdisable pin 1 = disabled, 0 = enabled, read only. d[6] stxdis soft transmit disable 1 = disabled; 0 = enabled. d[5] d[5] reserved re served - always write as zero. d[4] rsel reflects the state of the rsel pin 1 = high; 0 = low. d[3] srel soft rate select 1 = high (2gbps); 0 = low (1gbps). d[2] txflt reflects the state of the txfault pin 1 = high (fault); 0 = low (no fault). d[1] lo s loss of signal. reflects the state of the los pin 1 = high (loss of signal); 0 = low (no loss of signal). d[0] por MIC3002 power - on status 0 = por complete, analog data ready; 1 = por in progress. notes: 6. rxoph will contain measured data after one a/d conversion cycle.
micrel, inc. MIC3002 july 2007 48 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 alarm flags alarm status register 0 (alarm0) d[7] a7 read - only d[6] a6 read - only d[5] a5 read - only d[4] a4 read - only d[3] a3 read - only d[2] a2 read - only d[1] a1 read - only d[0] a1 read - only default value 0000 0000 b = 00 h (n o events pending) serial address a2 h byte address 112 = 70 h the power - up default value is 00 h . following the first a/d conversion, however, any of the bits may be set depending upon the results. bit(s) function operation d[7] a7 high temperature ala rm, temp > tmaxh 1 = condition exists, 0 = normal/ok. d[6] a6 low temperature alarm, temph< tmin 1 = condition exists, 0 = normal/ok. d[5] a5 high voltage alarm, vin > vmax 1 = condition exists, 0 = normal/ok. d[4] a4 low voltage alarm, vin < vmin 1 = c ondition exists, 0 = normal/ok. d[3] a3 high laser diode bias alarm, ibias > imax 1 = condition exists, 0 = normal/ok. d[2] a2 low laser diode bias alarm, ibias < imin 1 = condition exists, 0 = normal/ok. d[1] a1 high transmit optical power alarm, txop > txmax 1 = condition exists, 0 = normal/ok. d[0] a0 low transmit optical power alarm, txop < txmin 1 = condition exists, 0 = normal/ok. alarm status register 1 (alarm1) d[7] a15 read - only d[6] a14 read - only d[5] reserved d[4] reserved d[3] res erved d[2] reserved d[1] reserved d[0] reserved default value 0000 0000 b = 00 h (no events pending) serial address a2 h byte address 113 = 71 h the power - up default value is 00 h . following the first a/d conversion, however, any of the bits may be set depending upon the results. bit(s) function operation d[7] a15 high received power (overload) alarm, rxop > rxmax 1 = condition exists, 0 = normal/ok. d[6] a14 low received power (los) alarm, rxop < rxmin 1 = condition exists, 0 = normal/ok. d[5:0] reserved reserved - always write as zero.
micrel, inc. MIC3002 july 2007 49 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 warning flags warning status register 0 (warn0) d[7] w7 read - only d[6] w6 read - only d[5] w5 read - only d[4] w4 read - only d[3] w3 read - only d[2] w2 read - only d[1] w1 read - only d[0] w1 read - only default v alue 0000 0000 b = 00 h (no events pending) serial address a2 h byte address 116 = 74 h the power - up default value is 00 h . following the first a/d conversion, however, any of the bits may be set depending upon the results. bit(s) function operation d[7] w7 high temperature warning, temp > thigh 1 = condition exists, 0 = normal/ok. d[6] w6 low temperature warning, temp < tlow 1 = condition exists, 0 = normal/ok. d[5] w5 high voltage warning, vin > vhigh 1 = condition exists, 0 = normal/ok. d[4] w4 low voltage warning, vin < vlow 1 = condition exists, 0 = normal/ok. d[3] w3 high laser diode bias warning, ibias > ihigh 1 = condition exists, 0 = normal/ok. d[2] w2 low laser diode bias warning, ibias < ilow 1 = condition exists, 0 = normal/ok. d[1] w1 hi gh transmit optical power warning, txop > txhigh 1 = condition exists, 0 = normal/ok. d[0] w0 low transmit optical power warning, txop < txlow 1 = condition exists, 0 = normal/ok. warning status register 1 (warn1) d[7] w15 read - only d[6] w14 read -on ly d[5] read - only d[4] read - only d[3] read - only d[2] read - only d[1] read - only d[0] read - only default value 0000 0000 b = 00 h (no events pending) serial address a2 h byte address 117 = 75 h the power - up default value is 00 h . following the first a/d conversion, however, any of the bits may be set depending upon the results. bit(s) function operation d[7] w15 received power high warning, rxop > rxhigh 1 = condition exists, 0 = normal/ok. d[6] w14 received power low warning, rxop < rxmin 1 = c ondition exists, 0 = normal/ok. d[5:0] reserved reserved - always write as zero.
micrel, inc. MIC3002 july 2007 50 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 oem password entry (oempw) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write defa ult value 0000 0000 b = 00 h (reset to zero at power -on) serial address a2 h byte address if oemcfg5 - 2 = 0: 120 ? 123 = 78 h - 7b h (msb is 7b h if oemcfg5 - 2 = 1: 123? 126 = 7b h ? 7e h (msb is 7e h ) this four - byte field is for entry of the password r equired to access the oem area of the MIC3002?s memory and registers. a valid oem password will also permit access to the user areas of memory. the byte at address 123 (7b h ), 126 (7e h ) if omgfg5 bit2 =1, is the most significant byte. this field is compared to the four - byte oempwset field at serial address a6h, bytes 12 to 15. if the two fields match, access is allowed to the oem areas of the MIC3002 non - volatile memory at serial addresses a4 h and a6 h . the oem password is set by writing the new value into oe mpwset. the password comparison is performed following the write to the msb, address 7b h (7e h if oemcfg5 - 2 = 1). this byte must be written last! a four - byte burst - write sequence to address 78 h (7b h if oemcfg5 - 2 = 1) may be used as this will result in the m sb being written last. the new password will not take effect until after a power - on reset occurs or a warm reset is performed using the rst bit in oemcfg0. this allows the new password to be verified before it takes effect. this field is reset to all zeros at power on. any values written to these locations will be readable by the host regardless of the locked/unlocked status of the device . if oempwset is set to zero (00000000 h ), the MIC3002 will remain unlocked regardless of the contents of the oempw field. this is the factory default security setting. byte weight 3 oem password entry, most significant byte (address = 7bh resp. 7eh) 2 oem password entry, 2nd most significant byte (address = 7ah resp. 7dh) 1 oem password entry, 2nd least significant by te (address = 79h resp. 7ch) 0 oem password entry, least significant byte (address = 78h resp. 7bh) user password setting (usrpwset) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a2 h byte address 246 = f6 h this register is for setting the password required to access the user area of the MIC3002?s memory and registers. this field is compared to the usrpw field at se rial address a2 h , byte 247(f7h). if the two fields match, access is allowed to the user areas of the MIC3002 non - volatile memory at serial addresses a0h and a2h. if a valid user password has not been entered, writes to the serial id fields, usrctrl, and th e user scratchpad areas of a0 h and a2 h will not be allowed, and usrpwset will be unreadable (returns all zeroes). a user password is set by writing the new value into usrpwset. the new password will not take effect until after a power - on reset occurs or a warm reset is performed using the rst bit in oemcfg0. this allows the new password to be verified before it takes effect. this register is non - volatile and will be maintained through power and reset cycles. a valid user or oem password is required for acce ss to this register. otherwise, this register will read as 00 h . note: a valid oem password overrides the user password setting. if a valid oem password is currently in place, the user password will have no effect.
micrel, inc. MIC3002 july 2007 51 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 user password (usrpw) d[7] read/writ e d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a2 h byte address 247 = f7 h user passwords are entered in this field. this field is c ompared to the usrpwset field at serial address a2h, byte 246 (f6h). if the two fields match, access is allowed to the user areas of the MIC3002 non - volatile memory at serial addresses a0h and a2h. if a valid user password has not been entered, writes to t he serial id fields and user scratchpad areas of a0h and a2h will not be allowed and usrpwset will be unreadable (returns all zeroes). power - on hours d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h bytes address msb (pohh): 251 = fb h lsb (pohl): 252 = fc h the lower seven bits of pohh register contain the most - significant bits of the 15 - bit power - on hours measur ement. pohflt is an error flag. the value in pohh should be combined with the power - on hours, low byte, pohl, to yield the complete result. if pohflt is set, the power - on hour meter data has been corrupted and should be ignored. it is recommended that a t wo - byte (or more) sequential read operation be performed on pohh and pohl to insure coherency between the two registers. this register is non - volatile and will be maintained through power and reset cycle. pohh bit(s) function operation d[7] power -on ho urs fault flag 1 = fault; 0 = no fault. d[6:0] power - on hours, high byte non - volatile. data ready flags (datardy) d[7] trdy read/write d[6] vrdy read/write d[5] irdy read/write d[4] txrdy read/write d[3] rxdy read/write d[2] reserved d[1] reser ved d[0] reserved default value 0000 0000 b = 00 h serial address a6 h byte address 253 = fd h when the a/d conversion for a given parameter is completed and the results available to the host, the corresponding data ready flag will be set. the flag will be cleared when the host reads the corresponding result register. bit(s) function operation d[7] trdy temperature data ready flag 0 = old data; 1 = new data ready d[6] vrdy voltage data ready flag 0 = old data; 1 = new data ready d[5] irdy bias curre nt data ready flag 0 = old data; 1 = new data ready d[4] txrdy transmit power data ready flag 0 = old data; 1 = new data ready d[3] rxrdy receive power data ready flag 0 = old data; 1 = new data ready d[2:0] reserved reserved
micrel, inc. MIC3002 july 2007 52 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 user control register (usrctl) d[7] read/write d[6] porm read/write d[5] pors read/write d[4] ie read/write d[3] apcsel[1] read/write d[2] apcsel[0] read/write d[1] modsel[1] read/write d[0] modsel[0] read/write default value 0010 0000 b = 20 h serial address a2 h b yte address 255 = ff h if omcfg6 bit 2 = 0 222 = de h if omcfg6 bit 2 = 1 this register provides for control of the nominal apc setpoint and management of interrupts by the end - user. apcsel[1:0] select which of the apc setpoint registers, apcset0, apcset1, or apcset2 are used as the nominal automatic power control setpoint. ie must be set for any interrupts to occur. if porm is set, the power - on event will generate an interrupt and warm resets using rst will not generate a por interrupt. when a power - on inte rrupt occurs, assuming porm=1, pors will be set. pors will be cleared and the interrupt output de - asserted when usrctl is read by the host. if ie is set while /int is asserted, /int will be de- asserted. the host must still clear the various status flags by reading them. if porm is set following the setting of pors, pors will remain set, and /int will not be de - asserted, until usrctl is read by the host. porm, ie, and apcsel are non - volatile and will be maintained through power and reset cycles. a valid use r password is required for access to this register. bit function operation d[7] reserved always write as zero; reads undefined. d[6] porm power - on interrupt mask 1 = por interrupts enabled; 0 = disabled; read/write; non- volatile. d[5] pors power -on interrupt flag 1 = por interrupt occurred; 0 = no por interrupt; read - only. d[4] ie global interrupt enable 1 = enabled; 0 = disabled; read/write; non - volatile. d[3:2] apcsel selects apc setpoint register 00 = apcset0, 01 = apcset1, 10 = apcset2; 11 = reserved; read/write; non - volatile. d[1:0] modsel selects modulation setpoint register 00 = modset0, 01 = modset1, 10 = modset2, 11 = reserved; read/write; non volatile. oem configuration register 0 (oemcfg0) d[7] rst write only d[6] zone read/writ e d[5] dflt read only d[4] oe reserved d[3] modref reserved d[2] vaux[2] read/write d[1] vaux[1] read/write d[0] vaux[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 00 = 00 h a write to oemcfg0 will result in any a/d conversion in progress being aborted and the result discarded. the a/d will begin a new conversion sequence once the write operation is complete. all bits in oemcfg0 are non - volatile except dflt and rst. a valid oem password is required for access to this register. bit(s) function operation d[7] rst 0 = no action; 1 = reset; write - only. d[6] zone selects temperature zone. 0 = internal; 1 = external; non - volatile. d[5] dflt diode fault flag. 1 = diode fault; 0 = ok. d[4] oe output enable for shdn, v mod , 1 = enabled; 0 = hi - z; non - volatile.
micrel, inc. MIC3002 july 2007 53 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 and v bias . d[3] modref selects whether v mod is referenced to ground or v dd . 1 = v dd ; 0 = gnd; non - volatile. d[2:0] vaux[2:0] selects the voltage reported in vinh:vinl. 000 = v in ; 001 = v dda ; 010 = v bias ; 011 = v m od ; 100 = apcdac; 101 = moddac; 110 = fltdac; non - volatile oem configuration register 1 (oemcfg1) d[7] inv read/write d[6] gain read/write d[5] biasref read/write d[4] rfb[2] read/write d[3] rfb[1] read/write d[2] rfb[0] read/write d[1] srce re ad/write d[0] spol read/write default value 0000 0000 b = 00 h serial address a6 h byte address 1 = 01 h a write to oemcfg1 will result in any a/d conversion in progress being aborted and the result discarded. the a/d will begin a new conversion sequence once the write operation is complete. all bits in oemcfg1 are non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to this register. bit(s) function operation d[7] inv inverts the apc op - amp in puts. when set to ?0? the bias dac output is connected to the ?+?input and fb is connected to the ? ? ? input of the op amp. set to ?0? to use the adc feedback loop. 0 = emitter follower (no inversion); 1 = common emitter (inverted); read/write; non - volatil e. d[6] gain sets the feedback voltage range by changing the apcdac output swing; 0 -v ref for optical feedback, 0 -v ref /4 for electrical feedback. 1 = v ref /4 full scale; 0 = v ref full scale; read/write; non - volatile. d[5] biasref selects whether fb and vmp d are referenced to ground or v dd and selects feedback resistor termination voltage (v dda or gnda). 1 = v dd ; 0 = gnd; read/write; non - volatile. d[4:2] rfb[2:0] selects internal feedback resistance. (resistors will be terminated to v dda or gnda according t o biasref.) 000 = ; 001 = 800 ?, 010 = 1.6k ?, 011 = 3.2k ?, 100 = 6.4k ?, 101 = 12.8k ?, 110 = 25.6k ?, 111 = 51.2k ?; read/write; non - volatile. d[1] srce v bias source vs. sink drive. 1 = source (npn), 0 = sink (pnp); read/write; non - volatile. d[0] spol polarity of shut down output, shdn, when active. 1 = high; 0 = low; read/write; non - volatile.
micrel, inc. MIC3002 july 2007 54 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 oem configuration register 2 (oemcfg2) d[7] i2cadr[3] read/write d[6] i2cadr[2] read/write d[5] i2cadr[1] read/write d[4] i2cadr[0] read/write d[3] read/write d[2] r ead/write d[1] read/write d[0] read/write default value 1010 xxxx b = xx h (slave address = 1010xxx b ) serial address a6 h byte address 2 = 02 h caution: changes to i2cadr take effect immediately! any accesses following a write to i2cadr must be to the newly programmed serial bus address. a valid oem password is required for access to this register. this register is non - volatile and will be maintained through power and reset cycles. bit(s) function operation d[7:4] i2cadr[3:0] upper four msbs of the serial bus slave address; writes take effect immediately. read/write; non - volatile. d[3:0] reserved read/write; non - volatile. apc setpoint x (apcsetx) automatic power control setpoint (unsigned binary) used when apcsel[1:0] = 00 d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h bytes address apcset0: 3 = 03 h apcset1: 4 = 04 h apcset2: 5 = 05 h when a.p.c. is on, i.e., the apccal bit in oemcal0 is set, the value in apcsetx is added to the signed value taken from the a.p.c. look - up table and loaded into the vbias dac. when a.p.c. is off, the value in apcset is loaded directly into the vbias dac, bypassing the look - up table entirely. in either case, the vbias dac setting is reported in the vbias register. the apccfg bits determine the dac?s response to higher or lower numeric values. a valid oem password is required for access to this register. this register is non -v olatile and will be maintained through power and reset cycles. modulation setpoint x (modsetx) nominal v mod setpoint d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/wri te default value 0000 0000 b = 00 h serial address a6 h byte address modset0: 6 = 06 h modset1: 30 = 1e h modset2: 31 = 1f h when a.p.c. is on, the value corresponding to the current temperature is taken from the modlut look - up table, added to modset and lo aded into the v mod dac. this register is non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to this register.
micrel, inc. MIC3002 july 2007 55 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 i bias fault threshold (ibflt) bias current fault threshold d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 7 = 07 h a valid oem password is required for access to this register. th is register is non - volatile and will be maintained through power and reset cycles. a fault is generated if the bias current is higher than ibflt value set in this register. transmit power fault threshold (txflt) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 8 = 08 h a valid oem password is required for access to this register. this register is non - volatile and will be maintained through power and reset cycles. a fault is generated if the transmit power is higher than txflt value set in this register. loss - of - signal threshold (losflt) d[7] read/write d[6] read/write d[5] read/write d[4] read /write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 9 = 09 h a valid oem password is required for access to this register. this register is non - volatile and will be maintained through power and reset cycles. a fault is generated if the received power is lower than losflt value set in this register. byte function operation d[7:4] receive loss -of - signal threshold read/write; non - volatile. fault suppression timer (flttmr) fault suppression interval in increments of 0.5ms d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 10 = 0a h saturation faults are suppressed for a time, t flttmr , following laser turn - on. this avoids nuisance tripping while the apc loop starts up. the length of this interval is (flttmrx 0.5ms), typical. a value of zero will result in no fault s uppression. a valid oem password is required for access to this register. this register is non - volatile and will be maintained through power and reset cycles.
micrel, inc. MIC3002 july 2007 56 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 fault mask (fltmsk) d[7] oemim read/write d[6] pohe read/write d[5] reserved d[4] reserve d d[3] satmsk read/write d[2] txmsk read/write d[1] iamsk read/write d[0] dfmsk read/write default value 0000 0000 b = 00 h serial address a6 h byte address 11 = 0b h a valid oem password is required for access to this register. this register is non - volatile and will be maintained through power and reset cycles. bit function operation d[7] oemim oem interrupt mask bit 1 = masked; 0 = enabled; read/write; non - volatile. d[6] pohe oem power - on hour meter enable bit 1 = enabled; 0 = disabled; read/wr ite; non - volatile. d[5:4] d[5:4] reserved always write as zero; reads undefined. d[3] satmsk apc saturation fault mask bit 1 = masked; 0 = enabled; read/write; non - volatile. d[2] txmsk high tx optical power fault mask bit 1 = masked; 0 = enabled; read/ write; non - volatile. d[1] iamsk bias current high alarm mask bit 1 = masked; 0 = enabled; read/write; non - volatile. d[0] dfmsk diode fault mask bit 1 = masked; 0 = enabled; read/write; non - volatile. oem password setting (oempwset) d[7] read/write d[ 6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 12 - 15 = 0c h - 0f h ; 0c h = msb this four - byte field is the password requ ired for access to the oem area of the MIC3002?s memory and registers. the byte at address 12 (0c h ) is the most significant byte. this field is compared to the four - byte oempw field at serial address a2 h , byte 120 to 123 if omcfg6 - 2 = 0, or byte 123 to 126 if oemcfg6 - 2 = 1. if the two fields match, access is allowed to the oem areas of the MIC3002 non - volatile memory at serial addresses a4 h and a6 h . the oem password may be set by writing the new value into oempwset. the new password will not take effect unt il after a power - on reset occurs or a warm reset is performed using the rst bit in oemcfg0. this allows the new password to be verified before it takes effect. these registers are non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to this register. byte weight 3 oem password, most significant byte 2 oem password, 2nd most significant byte 1 oem password, 2nd least significant byte 0 oem password, least significant byte
micrel, inc. MIC3002 july 2007 57 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 oem calibrati on 0 (oemcal0) d[7] reserved d[6] fltdis read/write d[5] fspin read/write d[4] wrinh read/write d[3] apccal read/write d[2] frcint read/write d[1] frctxf read/write d[0] frclos read/write default value 0000 0000 b = 00 h serial address a6 h by te address 16 = 10 h a valid oem password is required for access to this register. bit function operation d[7] reserved always write as zero; reads undefined. d[6] fltdis fault comparator disable; inhibits output of fault comparators when set. 0 = fa ults enabled; 1 = disabled; read/write. d[5] fspin fault comparator ?spin -on- channel? mode select; do not enable adc and fc spin - on- channel modes simultaneously. 0 = normal operation; 1 = spin on channel; read/write. d[4] wrinh inhibit nvram write cycles . 0 = normal operation; 1 = inhibit writes; read/write. d[3] apccal selects apc calibration mode - dacs may be controlled directly. 0 = normal mode; 1 = calibration mode; read/write. d[2] frcint forces the assertion of /int 0 = normal operation; 1 = as serted; read/write. d[1] frctxf forces the assertion of txfault 0 = normal operation; 1 = asserted; read/write. d[0] fdclos forces the assertion of rxlos 0 = normal operation; 1 = asserted; read/write. oem calibration 1 (oemcal1) d[7] reserved d[6] adstp read/write d[5] adidl read/write d[4] 1shot read/write d[3] adspin read/write d[2] spin[2] read/write d[1] spin[1] read/write d[0] spin[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 17 = 11 h a valid oem passwo rd is required for access to this register. bit function operation d[7] reserved always write as zero; reads undefined. d[6] adstp stop adc halts the analog to digital converter 0 = normal operation; 1 = stopped; read/write. d[5] adidl adc idle flag 0 = busy; 1 = idle; read/write. d[4] 1shot triggers one - shot a/d conversion cycle 0 = normal operation; 1 = one - shot; read/write. d[3] adspin selects adc spin - on- channel mode; do not enable adc and fc spin - on - channel modes simultaneously 0 = normal oper ation; 1 = spin - on- channel; read/write. d[2], d[1], d[0] spin[2:0] adc and fault comparator (fc) channel select for spin - on- channel mode; do not enable adc and fc spin - on- channel modes simultaneously adc: 000 = temperature; 001 = voltage; 010 = vild; 011 = vmpd; 100 = vrx; fc: 001 = vild; 001 = vmpd; 010 = vrx; read/write.
micrel, inc. MIC3002 july 2007 58 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 oem calibration 1 ( lut index ) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 18 = 12h the look - up table index is derived from the current temperature measurement as follows: index = tavg / 2 where t avg (n) is the current average temperature. this register allows the current table index to be read by the host. the table base address must be added to lutindx to form a complete table index in physical memory. a valid oem password is required for access to this register. otherwise, reads are undefined. oem configuration 3 (oemcfg3) d[7] lutsel read/write d[6] txfpol read/write d[5] gpod read/write d[4] gpom read/write d[3] gpoc read/write d[2] txfin read/write d[1] losdis read/write d[0] intcal read/write default value 0000 1000 b = 08 h serial address a6 h byte address 19 = 13 h this register is non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to this register. gpod and gpoc are ignored when gpom = 0. txfpol is ignored if txfin = 0. bit function operation d[7] lutsel rx power look - up table input selection bit 1 = rx power; 0 = temperature; read/write; ignored if intcal = 0. d[6] txfpol txfin active polarity select; a fault is indicated when txfin = txfpol 0 = active - low; 1 = active - high; read/write; ignor ed if txfin = 0. d[5] gpod gpo output drive 0 = open drain; 1 = push - pull; read/write; ignored if gpom = 0. d[4] gpom gpo/rsout mode select 0 = rsout; 1 = gpo; read/write. d[3] gpoc gpo output control 0 = low; 1 = high; read/write; ignored if gpom = 0 . d[2] txfin txfin mode select 0 = shdn; 1 = txfin; read/write. d[1] losdis rxlos comparator disable 0 = enabled; 1 = disabled; read/write. d[0] intcal calibration mode select 0 = external calibration; 1 = internal calibration; read/write. bias dac setting (apcdac) current vbias setting d[7] read only d[6] read only d[5] read only d[4] read only d[3] read only d[2] read only d[1] read only d[0] read only default value 0000 0000 b = 00 h serial address a6 h byte address 20 = 14 h this register reflects (reads back) the value set in the apc register (apcset0, apcset1, or apcset2 whichever is selected). a valid oem password is required for access to this register.
micrel, inc. MIC3002 july 2007 59 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 modulation dac setting (moddac) current vmod setting d[7] read only d[6] read only d[5] read only d[4] read only d[3] read only d[2] read only d[1] read only d[0] read only default value 0000 0000 b = 00 h serial address a6 h byte address 21 = 15 h this register reflects (reads back) the value set in the modset register. a vali d oem password is required for access to this register. oem readback register (oemrd) d[7] reserved d[6] reserved d[5] reserved d[4] int read only d[3] apcsat read only d[2] ibflt read only d[1] txflt read only d[0] rsout read only default value 0000 0000 b = 00 h serial address a6 h byte address 22 = 16 h this register reflects (reads back) the status of the bits corresponding to the parameters defined below. a valid oem passwor d is required for access to this register. otherwise, reads are undefi ned and writes are ignored. bit function operation d[7:5] reserved always write as zero; reads undefined. d[4] int mirrors state of /int but active - high; not state of physical pin! 1 = interrupt; 0 = no interrupt. d[3] apcsat apc saturation fault co mparator output state 1 = fault; 0 = normal operation. d[2] ibflt state of ibias over - current fault comparator output 1 = fault; 0 = normal operation; read - only. d[1] txflt state of transmit power fault comparator output 1 = fault; 0 = normal operation; read - only. d[0] rsout state of the rate select output pin, rsout 1 = high; 0 = low; read - only. signal detect threshold (losfltn) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 23 = 17 h this register works in conjunction with the losflt register to control the operation of the loss of signal comparator. the comparator?s output, rxlos, is asserted when the input on vrx falls below the level in losflt. the output will then be de - asserted when the vrx signal rises above losfltn. the input signal is subject to scaling by the rxpot. if the los comparator is disabled, i.e., losdis = 1, this register is ignore d. a valid oem password is required for access to this register. this register is non - volatile and will be maintained through power and reset cycles.
micrel, inc. MIC3002 july 2007 60 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 rx eepot tap selection (rxpot) d[7] reserved d[6] reserved d[5] reserved d[4] read/write d[3] r ead/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 24 = 18 h this register is non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to these registers. bit(s) function operation d[7:5] reserved reserved. always write as zero; reads undefined. d[4:0] rxpot tap selection: 00000 = no divider action; pot disconnected 00001 = 31/32 00010 = 30/32 ? ? ? 11110 = 2/32 11111 = 1/32 read/write; non - volatile. oem configuration 4 (oemcfg4) d[7] reserved d[6] reserved d[5] reserved d[4] reserved d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 25 = 19 h this register is non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to these registers. bit(s) function operation d[7] allows warnings to assert txfault 0: warnings do not assert txfault 1: warnings assert txfault the rxpwr low warning flag does not assert txfault d[6] allows alarms to assert txfault 0: alarms do not assert txfault 1: alarms assert txfault the rxpwr low alarm flag does not assert txfault d[5] w arning latch 0: warnings flags are latched. they are cleared by reading the register or toggling txdisable. 1: warnings flags are not latched., i.e. they are set and reset with alarm condition. the flags are also cleared by reading the register or togg ling txdisable. d[4] alarm latch 0: alarms flags are latched. they are cleared by reading the register or toggling txdisable. 1: alarms flags are not latched., i.e. they are set and reset with alarm condition. the flags are also cleared by reading t he register or toggling txdisable.
micrel, inc. MIC3002 july 2007 61 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 i start [3:0] i start current level selection: 0000 = no i start current 0001 - 1111 = 0.375ma x i start [3:0] i start is used to speed up the laser start - up after a fault occurs. the charging current of the compensation ca p starts from i start instead of ramping up from 0. read/write; non - volatile. oem configuration 5 (oemcfg5) d[7] reserved d[6] reserved d[5] reserved d[4] reserved d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 26 = 1a h this register is non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to these registers. bit(s) function operation d[7] shdn output enabl e / disable 0: shdn is enabled. txfault will trigger shdn output 1: shdn is disabled. txfault has no effect on shdn output this applies when pin 7 is set as shdn output. d[6] temperature - compensation of the temperature used to access the l.u.t.s. 0: t he temperature used to index into the luts is not compensated (sensed temperature used) 1: the temperature used to index the luts is temperature - compensated (module case temperature used) d[5] temperature - compensation of the temperature result in the temp erature register. 0: the temperature result in the temperature register is not compensated (sensed temperature sed ) 1: the temperature result in the temperature register is compensated (module case temperature used) d[4] polarity of txfault 0: txfault is active high 1: txfault is active low d[3] smbus multipart support 0: multipart mode off 1: multipart mode on d[2] oem password location 0: a6h 120 - 123 (78h - 7bh) 1: a6h 123 - 126 (7bh - 7eh) d[1] smbus timeout enable / disable 0: smbus timeout enabl ed 1: smbus timeout disabled d[0] dacs reset 0: clear dacs when the laser is off 1: do not clear the dacs when laser is off
micrel, inc. MIC3002 july 2007 62 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 oem configuration 6 (oemcfg6) d[7] reserved d[6] reserved d[5] reserved d[4] reserved d[3] read/write d[2] read/write d[1 ] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 27 = 1b h this register is non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to these registers. bit(s) function operation d[5 -7] reserved d[4] txdisable debounce enable / disable 0: txdisable is not debounced 1: txdisable is debounced. glitches less than 5 ms are rejected. set the bit to 1 is a mechanical switch is used for txdisable. set to 0 for normal operation to assure compliance to the sfp msa. d[3] rxlos polarity 0: rxlos low for normal operation and high with a loss of signal condition. 1: rxlos high for normal operation (signal detected) and low with a loss of signal (no signal detected) condition. d[2] usrctrl register location 0: a2 255 (ffh) 1: a2 222 (deh) d[1] temperature resolution 0: temperature is measured to a resolution of 1oc 1: temperature is measured to a resolution of 0.5oc d[0] txfault clear mode 0: txfault remains set until txdisable is toggled 1: txfault is in continuous mode and follows the state of the faults. power - on hour meter data (pohdata) d[7] read/write d[6] read/write d[5] read/write d[4] read/write d[3] read/write d[2] read/write d[1] read/write d[0] read/write default value 0000 0000 b = 00 h serial address a6 h byte address 32- 39 = 20 h - 27 h these registers are used for backing up the poh result during power cycles. at power - up, the poh meter selects the larger of the two val ues as the initial count. incremental results are stored in alternate register pairs. the power - on hour meter may be reset or preset by writing to these registers. these registers are non - volatile and will be maintained through power and reset cycles. a v alid oem password is required for access to these registers. byte weight 3 poha, high - byte 2 poha, low - byte 1 pohb, high - byte 0 pohb, low - byte
micrel, inc. MIC3002 july 2007 63 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 oem scratchpad registers (scratchn) default value 0000 0000 b = 00 h serial address a6 h byte address 135- 143 (87 -8f h ) 156- 159 (9c -9f h ) 172- 175 (ac -af h ) 188- 191 (bc -bf h ) 204- 207 (cc -cf h ) 222- 250 (de - fa h ) the scratchpad registers are general - purpose non - volatile memory locations. they can be freely read from and written to any time the MIC3002 is in oem m ode. rx power look - up table (rxlutn) default value 0000 0000 b = 00 h serial address a6 h byte address 40- 71 = 28 h - 47 h these registers are non - volatile and will be maintained through power and reset cycles. a valid oem password is required for acce ss to these registers. bytes definition rxslp0h rx slope 0, high byte. rxslp0l rx slope 0, low byte. rxoff0h rx offset 0, high byte. rxoff0l rx offset 0, low byte. rxslp1h rx slope 1, high byte. rxslp1l rx slope 1, low byte. rxoff1h rx offset 1, high byte. rxoff1l rx offset 1, low byte. ? ? ? ? ? ? rxslp7h rx slope 7, high byte. rxslp7l rx slope 7, low byte. rxoff7h rx offset 7, high byte. rxoff7l rx offset 7, low byte. calibration constants (caln) default value 0000 0000 b = 00 h seri al address a6 h byte address 74 - 87 = 4a h - 57h these registers are non - volatile and will be maintained through power and reset cycles. a valid oem password is required for access to these registers.
micrel, inc. MIC3002 july 2007 64 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 bytes definition vslp0h voltage slope, high byt e. vslp0l voltage slope, low byte. voffh voltage offset, high byte. voff0l voltage offset, low byte. islp0h bias current slope, high byte. islp0l bias current slope, low byte. ioffh bias current offset, high byte. ioff0l bias current offset, low byt e. txslph tx power slope, high byte. txslpl tx power slope, low byte. txoffh tx power offset, high byte. txoffl tx power offset, low byte. manufacturer id register (mfg_id) identifies micrel as the manufacturer of the device. always returns 2ah d[7 ] read only d[6] read only d[5] read only d[4] read only d[3] read only d[2] read only d[1] read only d[0] read only default value 0010 1010 b = 2a h serial address a6 h byte address 254 = fe h the value in this register, in combination with the dev_i d register, serve to identify the MIC3002 and its revision number to software. this register is read - only. bit(s) function operation d[7:0] identifies micrel as the manufacturer of the device. always returns 2a h . read only. always returns a h device id register (dev_id) d[7] read only d[6] read only d[5] read only d[4] read only d[3] read only d[2] read only d[1] read only d[0] read only MIC3002 device id always reads 0 at d[5 - 7] and 1 at d[4] die revision default value 0001 xxxx b = 1x h ser ial address a6 h byte address 255 = ff h the value in this register, in combination with the mfg_id register, serve to identify the MIC3002 and its revision number to software. this register is read - only.
micrel, inc. MIC3002 july 2007 65 m9999 -073107 -b hbwhelp@micrel.com or (408) 955 - 1690 package information 24- pin qfn micre l, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http:/www.micrel.com the information furnished by micrel in this data sheet is believed to be accurate and reliable. however, no responsibility is a ssumed by micrel for its use. micrel reserves the right to change circuitry and specifications at any time without notification to the customer. micrel products are not designed or authorized for use as components in life support appliances, devices or sy stems where malfunction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchas er?s own risk and purchaser agrees to fully indemnify micre l for any damages resulting from such use or sale. ? 2007 micrel, incorporated.

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